SDI II Intel® FPGA IP User Guide

ID 683133
Date 4/04/2022
Public

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8.2. Design Examples for Arria V, Cyclone V, and Stratix V Devices

The SDI II design example for Arria V, Cyclone V or Stratix V devices are synthesizable.

Figure below illustrates the generated design example entity and simulation testbench for Arria V, Cyclone V, and Stratix V devices. This design example consists of a video pattern generator, transceiver reconfiguration controller, reconfiguration management, loopback path, and various SDI blocks occupying two transceiver channels.

Figure 43. Design Example Entity and Simulation Testbench


Figure 44. Design Example Entity and Simulation Testbench for HD-SDI Dual Link to 3G-SDI (Level B) ConversionThe figure below illustrates the generated design example entity and simulation testbench when you generate HD-SDI dual link receiver with Convert HD-SDI dual link to 3G-SDI (level B) option enabled.


Figure 45. Design Example Entity and Simulation Testbench for 3G-SDI (Level B) to HD-SDI Dual Link ConversionThe figure below illustrates the generated design example entity and simulation testbench when you generate 3G-SDI or triple rate SDI receiver with Convert 3G-SDI (level B) to HD-SDI dual link option enabled.


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