SDI II Intel® FPGA IP User Guide

ID 683133
Date 4/04/2022
Public

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8.2.3. Simulating the SDI II IP Core Design

After design generation, the files located in the simulation testbench directory are available for you to simulate your design.

The SDI II IP core supports the following EDA simulators listed in the table below.

Table 34.  Supported EDA Simulators

Simulator

Supported Platform

Supported Language

ModelSim SE*

Windows*/Linux*

VHDL and Verilog HDL

Questa*-Intel® FPGA Edition

Windows/Linux

Verilog HDL

Synopsys VCS/VCS MX

Windows/Linux

Verilog HDL

Aldec Riviera-PRO

Linux

Verilog HDL

To simulate the design using the ModelSim SE* or Questa*-Intel® FPGA Edition simulator, follow these steps:

  1. Start the simulator.
  2. On the File menu, click Change Directory > Select <simulation folder>/<preferred HDL>/mentor.
  3. Run the provided run_sim.tcl script. This file compiles the design and runs the simulation automatically. It provides a pass/fail indication on completion.

To simulate the design using the VCS/VCS MX simulator (in Linux), follow these steps:

  1. Start the VCS/VCS MX simulator.
  2. On the File menu, click Change Directory > Select <simulation folder>/<preferred HDL>/synopsys.
  3. Run the provided run_vcs.sh (in VCS) or run_vcsmx.sh (in VCSMX) script. This file compiles the design and runs the simulation automatically. It provides a pass/fail indication on completion.

To simulate the design using the Aldec Riviera-PRO simulator, follow these steps:

  1. Start the Aldec Riviera-PRO simulator.
  2. On the File menu, click Change Directory > Select <simulation folder>/<preferred HDL>/aldec.
  3. Run the provided run_riviera.tcl script. This file compiles the design and runs the simulation automatically. It provides a pass/fail indication on completion.

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