SDI II Intel® FPGA IP User Guide

ID 683133
Date 4/04/2022

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5.4.5. Dynamic TX Clock Switching for Arria V, Cyclone V, and Stratix V Devices

The dynamic TX clock switching feature allows you to dynamically switch between NTSC and PAL transceiver data rates for all video standards except SD-SDI.

Note: For information about dynamic TX clock switching for Intel® Arria® 10, Intel® Cyclone® 10 GX, and Intel® Stratix® 10 devices, refer to the respective design example user guides.
The dynamic TX clock switching enables an SDI video equipment to operate on NTSC or PAL. You can choose to switch the TX clock through one of these two methods:
  • Instantiate an alternate TX PLL and supply two different clocks to the two PLLs. Switch between the primary PLL and the alternate PLL for transmission.
  • Use the primary PLL with two reference input clocks. The PLL switches between these two clocks for transmission.

To implement this feature, you are required to provide two reference clocks (xcvr_refclk and xcvr_refclk_alt) to the SDI II IP core. The frequency of the reference clocks must be assigned to 148.5 MHz and 148.35 MHz in any assignment order.

The TX PLL select signal (ch1_{tx/du}_tx_pll_sel) is an input control signal that you provide to the core and the transceiver reconfiguration controller to select the desired clock input for the Native PHY IP core.
  • Set ch1_{tx/du}_tx_pll_sel to 0 to select xcvr_refclk
  • Set ch1_{tx/du}_tx_pll_sel to 1 to select xcvr_refclk_alt
To dynamically switch between the two reference clocks, you need to implement a simple handshaking mechanism. The handshake is initiated when the reconfiguration request signal (ch1_{tx/du}_tx_start_reconfig) is asserted high. This signal must remain asserted until the reconfiguration process completes. The reconfiguration process completes when the reconfiguration done signal (ch1_{tx/du}_tx_reconfig_done) is asserted high. The TX PLL select signal (ch1_{tx/du}_tx_pll_sel) needs to be stable throughout the reconfiguration process.

To complete the handshaking process, you must deassert the reconfiguration request signal (ch1_{tx/du}_tx_start_reconfig) upon assertion of the reconfiguration done signal (ch1_{tx/du}_tx_reconfig_done). The dynamic TX clock switching only takes effect after the tx_rst is asserted high and deasserted low accordingly.

Figure 31. Hardware Implementation of the Dynamic TX Clock Switching FeatureThis figure shows the TX clock switching feature with two TX PLLs.

Figure 32. Dynamic TX Clock Switching Timing Diagram

The table below describes the behavior of the dynamic switching feature when you initiate a handshaking process (with reference to the timing diagram).

Table 16.   Dynamic Switching Behavior During a Handshaking Process
Case Description
1 The handshaking process attempts to switch to select xcvr_refclk_alt. tx_clkout successfully locks to xcvr_refclk_alt (148.35 MHz).
2 The handshaking process attempts to switch to select xcvr_refclk. tx_clkout successfully locks to xcvr_refclk (148.5 MHz).
3 The handshaking process attempts to switch to select xcvr_refclk_alt. The switching fails because ch1_{tx/du}_tx_pll_sel changes from 1 to 0 before the assertion of ch1_{tx/du}_tx_start_reconfig. Therefore, tx_clkout remains locked to xcvr_refclk (148.5MHz).

Implementing TX PLL and Reference Clock Switching

To implement the TX PLL and reference clock switching, follow these steps:
  1. Trigger the tx_pll_sel signal to the desired reference clock: 0 for 148.5 or 1 for 148.35 MHz.
  2. Assert the tx_start_reconfig signal at the same clock cycle. You may assert the signal at the next clock cycle as long as you do not toggle back the tx_pll_sel signal.
  3. Keep the tx_start_reconfig signal asserted until the tx_reconfig_done signal asserts.
  4. Deassert the tx_start_reconfig signal and assert the tx_rst signal at the next cycle.
  5. The TX clock (tx_clk) should run at the new frequency now.

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