SDI II Intel® FPGA IP User Guide

ID 683133
Date 4/04/2022
Public

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Document Table of Contents

5.1.2. Receiver

The receiver performs the following functions:

  • Video standard detection
  • Video rate detection
  • NRZI decoding and descrambling
  • Word alignment
  • Demultiplex data links
  • Video timing flags extraction
  • HD-SDI LN extraction
  • HD-SDI CRC
  • Payload ID extraction
  • Synchronizing data streams
  • Accessing transceiver
  • Identifying and tracking of ancillary data
  • Sync bit removal

The block diagrams below illustrate the SDI II IP core receiver (simplex) data path for each supported video standard.

Figure 11. SD-SDI Receiver Data Path Block Diagram


Figure 12. HD-SDI Receiver Data Path Block Diagram


Figure 13. 3G-SDI Receiver Data Path Block Diagram


Figure 14. Dual Rate SDI Receiver Data Path Block Diagram


Figure 15. Dual Link HD-SDI Receiver Data Path Block Diagram


Figure 16. Triple Rate SDI Receiver Data Path Block Diagram


Figure 17. Multi Rate (up to 12G-SDI) Receiver Data Path Block Diagram
Note: The receive block shown in the diagram is the simplified version of the transmit block in the Triple Rate SDI Receiver Data Path Block Diagram.

For bidirectional or duplex mode, the protocol and PHY management & adapter blocks remain the same for each direction, except the Native PHY IP core, which is configured in duplex mode. The figure below illustrates the data path of a SD-SDI duplex mode.

Figure 18. SD-SDI Duplex Mode Block Diagram


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