SDI II Intel® FPGA IP User Guide

ID 683133
Date 4/04/2022
Public

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7.1.3.6. SD-SDI Timing Jitter With External VCXO Which Receive FVH Sync Signals

There is one limitation in SD-SDI where the FVH sync output signals from Rx core is not good enough to clock external VCXO for genlocking purpose. To workaround the problem, Intel recommends to use an external sync separator to generate the FVH sync signals to the external VCXO. Alternatively, you can use to parallel loopback without external VCXO design example.

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