|Intel® Quartus® Prime Design Suite 21.4|
|IP Version 4.0.0|
- Setting up the required reference clocks. The system clock must be constant across all profiles in a selected dynamic reconfiguration group.
- Selecting the appropriate clocks input for each of the MAC, FEC, PCS, and transceiver blocks
- Setting the multiplexers to select the appropriate control and data path for MAC/PCS/PMA/FEC-direct modes
- Nios® -based dynamic reconfiguration: This flow includes the inter protocol switching, such as Ethernet to CPRI protocols, and intra protocol link characteristic changes, such as CPRI data rate changes. A client application or an Intel® Quartus® Prime Nios® utility triggers the dynamic reconfiguration. When triggered, the Nios® performs the low level configuration register programming for various functional blocks.
- Host software-based dynamic reconfiguration: This flow includes the inter protocol switching, such as Ethernet to CPRI protocols, or intra protocol link characteristic changes, such as CPRI data rate changes. The host software runs on an Intel® Xeon® or Arm* processor and performs low level configuration register programming for various functional blocks in the FPGA fabric, such as EMIB, and the tile directly. For this use case, you must refer to the appropriate F-tile based collaterals to build your own solution.
- Individual protocols-based dynamic reconfiguration: This flow includes intra protocol link characteristics changes such as link width, transmitter swing changes, data rate switching, and mode changes such as FEC types. The individual protocols such as HDMI, DisplayPort, or SDI include built-in state machines and controllers to dynamically change transceiver configuration registers when the link characteristics change.
This document describes the NIOS-based dynamic reconfiguration through the F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP. The document also specifies the dynamic reconfiguration programming sequences as references for the software-based dynamic reconfiguration. The individual protocol-based dynamic reconfiguration is not part of this document.