F-Tile SDI II Intel® Agilex™ FPGA IP Design Example User Guide

Download PDF
ID 710496
Date 1/28/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Document Table of Contents x
1. F-Tile SDI II Intel® Agilex™ FPGA IP Design Example Quick Start Guide 2. Design Example Detailed Description 3. Document Revision History for the F-Tile SDI II Intel® Agilex™ Design Example User Guide
1. F-Tile SDI II Intel® Agilex™ FPGA IP Design Example Quick Start Guide x
1.1. Directory Structure 1.2. Generating the Design 1.3. Simulating the Design 1.4. Compiling and Testing the Design in Hardware 1.5. Design Example Parameters
2. Design Example Detailed Description x
2.1. Features 2.2. Hardware and Software Requirements 2.3. Functional Description 2.4. Simulation
2.3. Functional Description x
2.3.1. Design Components 2.3.2. Clocking Scheme
2.3.2. Clocking Scheme x
2.3.2.1. Clocking Scheme Component
2.4. Simulation x
2.4.1. Testbench Components 2.4.2. Test Description 2.4.3. Hardware Testing 2.4.4. Signal
2.4.3. Hardware Testing x
2.4.3.1. Parallel loopback 2.4.3.2. Serial loopback
1. F-Tile SDI II Intel® Agilex™ FPGA IP Design Example Quick Start Guide
2. Design Example Detailed Description
3. Document Revision History for the F-Tile SDI II Intel® Agilex™ Design Example User Guide

1. F-Tile SDI II Intel® Agilex™ FPGA IP Design Example Quick Start Guide

Updated for:
Intel® Quartus® Prime Design Suite 21.4
IP Version 19.2.0
The SDI II Intel® FPGA IP design examples for Intel® Agilex™ F-tile devices feature a simulating testbench and a hardware design that supports compilation and hardware testing.
When you generate a design example, the parameter editor automatically creates the files necessary to simulate, compile, and test the design in hardware.
Note: The support for 21.4 Intel® Agilex™ SDI II Design Example hardware is preliminary and only supports static rate.
Figure 1. Development Stages
Level Two Title