F-Tile SDI II Intel® Agilex™ FPGA IP Design Example User Guide

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ID 710496
Date 1/28/2022
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Document Table of Contents
Document Table of Contents x
1. F-Tile SDI II Intel® Agilex™ FPGA IP Design Example Quick Start Guide 2. Design Example Detailed Description 3. Document Revision History for the F-Tile SDI II Intel® Agilex™ Design Example User Guide
1. F-Tile SDI II Intel® Agilex™ FPGA IP Design Example Quick Start Guide x
1.1. Directory Structure 1.2. Generating the Design 1.3. Simulating the Design 1.4. Compiling and Testing the Design in Hardware 1.5. Design Example Parameters
2. Design Example Detailed Description x
2.1. Features 2.2. Hardware and Software Requirements 2.3. Functional Description 2.4. Simulation
2.3. Functional Description x
2.3.1. Design Components 2.3.2. Clocking Scheme
2.3.2. Clocking Scheme x
2.3.2.1. Clocking Scheme Component
2.4. Simulation x
2.4.1. Testbench Components 2.4.2. Test Description 2.4.3. Hardware Testing 2.4.4. Signal
2.4.3. Hardware Testing x
2.4.3.1. Parallel loopback 2.4.3.2. Serial loopback
1. F-Tile SDI II Intel® Agilex™ FPGA IP Design Example Quick Start Guide
2. Design Example Detailed Description
3. Document Revision History for the F-Tile SDI II Intel® Agilex™ Design Example User Guide

2.4.2. Test Description

The simulation only checks for the assertion of trs_locked signal and the number of transceiver reconfiguration triggered after every video standard switching.

For single-rate design, there is one video standard being tested:

  • HD single-rate – HD
  • 3G single-rate – 3G Level A 10-bit Multiplex
  • 12G single-rate - 12G 10-bit Multiplex Type 1
Figure 22. Simulation Waveform
Table 12.  Signals Description
Testbench signal Description
/tb_top/tb_rx_checker/rx_std Video standard keep switching after obtaining lock signal
/tb_top/tb_rx_checker/align_locked Lock signals from IP core
/tb_top/tb_rx_checker/trs_locked

A successful simulation ends with the following message:

Level Two Title