SDI II Intel® FPGA IP User Guide

ID 683133
Date 10/08/2021
Public

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7.1.2.8. Routing Transceiver Reference Clock Pins to Core Logic in Intel® Stratix® 10 Devices

Due to the number of clock paths available from the transceiver tile to the core logic, you must assign a clock from the GPIO pin to feed the rx_coreclk and other processing blocks which run on core logic. You must make the clock assignment if the following conditions apply:
  • Uses channel 0 and channel 3 in a transceiver bank.
  • SDI RX and TX cores are placed in either one of these channels.
  • Both SDI RX and RX cores are in multi-rate mode.

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