1. SDI II IP Core Quick Reference 2. SDI II IP Core Overview 3. SDI II IP Core Getting Started 4. SDI II IP Core Parameters 5. SDI II IP Core Functional Description 6. SDI II IP Core Signals 7. SDI II IP Core Design Considerations 8. SDI II IP Core Testbench and Design Examples 9. SDI II Intel® FPGA IP User Guide Archives 10. Document Revision History for the SDI II Intel® FPGA IP User Guide
5.3.1. Insert Line 5.3.2. Insert/Check CRC 5.3.3. Insert Payload ID 5.3.4. Match TRS 5.3.5. Scrambler 5.3.6. TX Sample 5.3.7. Clock Enable Generator 5.3.8. RX Sample 5.3.9. Detect Video Standard 5.3.10. Detect 1 and 1/1.001 Rates 5.3.11. Transceiver Controller 5.3.12. Descrambler 5.3.13. TRS Aligner 5.3.14. 3Gb Demux 5.3.15. Extract Line 5.3.16. Extract Payload ID 5.3.17. Detect Format 5.3.18. Sync Streams 5.3.19. Convert SD Bits 5.3.20. Insert Sync Bits 5.3.21. Remove Sync Bits
22.214.171.124. Changing RX CDR Reference Clock in Transceiver Native PHY IP Core 126.96.36.199. Merging Simplex Mode Transceiver in the Same Channel 188.8.131.52. Using Generated Reconfiguration Management for Triple and Multi Rates 184.108.40.206. Ensuring Independent RX and TX Operations in the Same Channel 220.127.116.11. Potential Routing Problem During Fitter Stage in Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices 18.104.22.168. Unconstrained Clocks in SDI Multi-Rate RX Using Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices 22.214.171.124. Unused Transceiver Channels 126.96.36.199. Routing Transceiver Reference Clock Pins to Core Logic in Intel® Stratix® 10 Devices
2.2. Device Family Support
|Device Family||Support Level|
|Intel® Stratix® 10—L-tile (from Intel® Quartus® Prime Pro Edition version 19.1 onwards)||Final|
|Intel® Stratix® 10—H-tile (from Intel® Quartus® Prime Pro Edition version 17.1 onwards)||Final|
|Intel® Cyclone® 10 GX (from Intel® Quartus® Prime Pro Edition version 17.1.1 onwards)||Final|
|Intel® Arria® 10 (from Intel® Quartus® Prime version 14.0A10 onwards)||Final|
|Arria V GZ and Cyclone V (from Intel® Quartus® Prime Standard Edition version 13.0 onwards)||Final|
|Arria V GX/GT/SX/ST and Stratix V (from Intel® Quartus® Prime Standard Edition version 12.1 onwards)||Final|
The following terms define device support levels for Intel FPGA IP cores:
- Advance support—the IP core is available for simulation and compilation for this device family. Timing models include initial engineering estimates of delays based on early post-layout information. The timing models are subject to change as silicon testing improves the correlation between the actual silicon and the timing models. You can use this IP core for system architecture and resource utilization studies, simulation, pinout, system latency assessments, basic timing assessments (pipeline budgeting), and I/O transfer strategy (data-path width, burst depth, I/O standards tradeoffs).
- Preliminary support—the IP core is verified with preliminary timing models for this device family. The IP core meets all functional requirements, but might still be undergoing timing analysis for the device family. It can be used in production designs with caution.
- Final support—the IP core is verified with final timing models for this device family. The IP core meets all functional and timing requirements for the device family and can be used in production designs.
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