SDI II Intel® FPGA IP User Guide

ID 683133
Date 10/08/2021
Public

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5.3.13. TRS Aligner

The TRS aligner word aligns the descrambled receiver data until the bit order of the output data and the original video data are the same. The EAV and SAV sequences determine the correct word alignment.

Table 14.  EAV and SAV SequencesThis table lists the sequence pattern for each video standard.

Video Standard

EAV and SAV Sequences

SD-SDI

3FF 000 000

HD-SDI

3FF 3FF 000 000 000 000

3G-SDI Level A 10-bit Multiplex

3FF 3FF 000 000 000 000

3G-SDI Level B 10-bit Multiplex

3FF 3FF 3FF 3FF 000 000 000 000 000 000 000 000

6G-SDI 10-bit Multiplex Type 1

3FF 3FF 3FF 3FF 000 000 000 000 000 000 000 000

6G-SDI 10-bit Multiplex Type 2

3FF 3FF 3FF 3FF 3FF 3FF 3FF 3FF 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000

12G-SDI 10-bit Multiplex Type 1

3FF 3FF 3FF 3FF 3FF 3FF 3FF 3FF 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000

12G-SDI 10-bit Multiplex Type 2

3FF 3FF 3FF 3FF 3FF 3FF 3FF 3FF 3FF 3FF 3FF 3FF 3FF 3FF 3FF 3FF 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000

The TRS aligner determines the correct word alignment for the data. The aligner looks for three consecutive TRSs with the same alignment and then stores that alignment. If the aligner subsequently detects two consecutive TRSs with a different alignment, then it stores this new alignment.

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