SDI II Intel® FPGA IP User Guide

ID 683133
Date 10/08/2021
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

6.1. SDI II IP Core Resets and Clocks

Table 16.  Resets and Clock Signals
Signal Width Direction Description
tx_rst 1 Input

Reset signal for the transmitter. This signal is active high and level sensitive.

This signal must be synchronous to tx_pclk clock domain (for Intel® Arria® 10, Intel® Cyclone® 10 GX, and Intel® Stratix® 10 devices) or tx_coreclk (for Arria V, Cyclone V, and Stratix V devices).

pll_powerdown_in 1N Input

When asserted, this signal resets TX PLL. You must connect this signal to pll_powerdown_out.

You can connect this signal from multiple SDI instances to pll_powerdown_out of one of the SDI instances to merge the PLL in these instances.

For TX PLL merging, pll_powerdown_in and xcvr_refclk from multiple instances must share the same source.

N = Number of PLLs in the core—1 (default) or 2 (when TX PLL switching enabled)

Note: Not applicable for these settings:
  • In protocol only mode.
  • For Intel® Arria® 10, Intel® Cyclone® 10 GX, and Intel® Stratix® 10 devices.

If you enabled the Dynamic Tx clock switching parameter, your design requires XCVR_TX_PLL_RECONFIG_GROUP QSF assignment. Refer to the Transceiver PHY IP Core User Guide for more information.

pll_powerdown_out 1N Output

When asserted, this signal resets the selected TX PLL.

N = Number of PLLs in the core—1 (default) or 2 (when TX PLL switching enabled)

Note: Not applicable for these settings:
  • In protocol only mode.
  • For Intel® Arria® 10, Intel® Cyclone® 10 GX, and Intel® Stratix® 10 devices.
rx_rst

1

Input

Reset signal for the receiver. This signal is active high and level sensitive. This reset signal must be synchronous to the rx_coreclk or rx_coreclk_hd clock domain.

rx_rst_proto_in

1

Input

Receiver protocol reset signal. This signal must be driven by the rx_rst_proto_out reset signal from the transceiver block.
Note: Applicable for receiver protocol configuration only (Arria V, Cyclone V, and Stratix V devices).
rx_rst_proto_in_b

1

Input

Receiver protocol reset signal for link B. This signal must be driven by the rx_rst_proto_out_b reset signal from the transceiver block.
Note: For HD-SDI dual link receiver protocol configuration only.
rx_rst_proto_out

1

Output

Reset the receiver protocol downstream logic. This generated signal is synchronous to rx_clkout clock domain and must be used to drive the rx_rst_proto_in signal of the receiver protocol block.

rx_rst_proto_out_b

1

Output

Reset the receiver protocol downstream logic.
Note: For HD-SDI dual link receiver transceiver configuration only.
trig_rst_ctrl

1

Output

Reset output signal to the transceiver reset controller to reset the transceiver. This signal is synchronous to the rx_coreclk or rx_coreclk_hd clock domain.
Note: Applicable only for Intel® Arria® 10, Intel® Cyclone® 10 GX, and Intel® Stratix® 10 devices.
tx_pclk

1

Input

Transmitter core parallel clock signal. This clock signal must be driven by the by parallel output clock from TX transceiver.

  • SD-SDI = 148.5 MHz
  • HD-SDI = 74.25 MHz or 74.175 MHz, depending on video frame rate
  • 3G-SDI = 148.5 MHz or 148.35 MHz, depending on video frame rate
  • HD-SDI Dual Link = 74.25 MHz or 74.175 MHz, depending on video frame rate
  • Dual Rate = 148.5 MHz or 148.35 MHz, depending on video frame rate
  • Triple Rate = 148.5 MHz or 148.35 MHz, depending on video frame rate
  • Multi Rate (up to 12G-SDI) = 148.5 MHz or 148.35 MHz, depending on video frame rate
tx_coreclk

1

Input

148.5-MHz or 148.35-MHz transmitter core clock signal. This clock source must be always stable and can be shared with xcvr_refclk.

Note: Not applicable for these settings:
  • In protocol only mode.
  • If the selected transceiver reference clock frequency is 74.25 MHz/74.175 MHz.
  • For Intel® Arria® 10, Intel® Cyclone® 10 GX, and Intel® Stratix® 10 devices.
tx_coreclk_hd

1

Input

74.25-MHz or 74.175-MHz transmitter core clock signal. This clock source must be always stable and can be shared with xcvr_refclk.

Note: Applicable for HD-SDI and HD-SDI dual link modes only if the selected transceiver reference clock frequency is 74.25 MHz/74.175 MHz. Not applicable for Intel® Arria® 10, Intel® Cyclone® 10 GX, and Intel® Stratix® 10 devices.
rx_coreclk

1

Input

Receiver core clock signal. You can set the following frequencies:
  • 148.5-MHz or 148.35-MHz: Applicable for all configurations.
  • 297.0 MHz or 296.70 MHz: Applicable only for Intel® Arria® 10, Intel® Cyclone® 10 GX, and Intel® Stratix® 10 devices in multi-rate modes.

This clock source must be stable and there are no required relationships with any other clocks. The clock source can be asynchronous or synchronous to any transceiver's clock.

Note: Not applicable if the selected transceiver reference clock frequency is 74.25 MHz/74.175 MHz.
For Intel® Stratix® 10 devices, assign this clock to a GPIO clock instead of a transceiver reference clock pin if the following conditions apply:
  • Uses channel 0 and channel 3 in a transceiver bank.
  • SDI RX and TX cores are placed in either one of these channels.
  • Both SDI RX and RX cores are in multi-rate mode.
rx_coreclk_hd

1

Input

74.25-MHz or 74.175-MHz receiver core clock signal. This clock source must be always stable and can be shared with xcvr_refclk.

This clock source must be stable and there are no required relationships with any other clocks. The clock source can be asynchronous or synchronous to any transceiver's clock.

Note: Applicable for HD-SDI and HD-SDI dual link modes only if the selected transceiver reference clock frequency is 74.25 MHz/74.175 MHz. Not applicable for Intel® Arria® 10, Intel® Cyclone® 10 GX, and Intel® Stratix® 10 devices.
rx_clkin

1

Input

Receiver protocol clock input. This signal must be driven by the rx_clkout clock signal from the transceiver block.
  • SD-SDI = 148.5 MHz
  • HD-SDI = 74.25 MHz or 74.175 MHz, depending on video frame rate
  • 3G-SDI = 148.5 MHz or 148.35 MHz, depending on video frame rate
Note: For receiver protocol configuration only. Not applicable for Intel® Arria® 10, Intel® Cyclone® 10 GX, and Intel® Stratix® 10 devices.
rx_clkin_b

1

Input

Receiver protocol clock input for link B. This signal must be driven by the rx_clkout_b clock signal from the transceiver block ((74.25 MHz or 74.125 MHz, depending on video frame rate).
Note: For HD-SDI dual link receiver protocol configuration only. Not applicable for Intel® Arria® 10, Intel® Cyclone® 10 GX, and Intel® Stratix® 10 devices.
rx_clkin_smpte372

1

Input

Clock input for HD-SDI dual link to 3G-SDI (level B) and 3G-SDI (level B) to HD-SDI dual link operations.

  • HD-SDI dual link to 3G-SDI (level B) = 148.5 MHz or 148.35 MHz
  • 3G-SDI (level B) to HD-SDI dual link = 74.25 MHz or 74.175 MHz
xcvr_rxclk 1 Input

Receiver parallel clock input. Driven by rx_pma_div_clkout (for multi-rate modes) or rx_clkout (for other modes) from the transceiver.

  • SD-SDI = 148.5 MHz
  • HD-SDI = 74.25 MHz or 74.175 MHz, depending on video frame rate
  • 3G-SDI = 148.5 MHz or 148.35 MHz, depending on video frame rate
  • 6G-SDI = 148.5 MHz or 148.35 MHz, depending on video frame rate
  • 12G-SDI = 148.5 MHz or 148.35 MHz, depending on video frame rate
Note: Applicable only for Intel® Arria® 10, Intel® Cyclone® 10 GX, and Intel® Stratix® 10 devices.
xcvr_refclk

1

Input

Reference clock signal for the transceiver. Only a single reference clock frequency is required to support both integer and fractional frame rates for RX CDR.

The clock source must be stable. It must be a free running clock connected to the transceiver clock pin.

  • SD-SDI = 148.5 MHz
  • HD-SDI = 74.25 MHz, 74.175 MHz, 148.5 MHz, or 148.35 MHz
  • 3G-SDI = 148.5 MHz or 148.35 MHz
  • HD-SDI Dual Link: 74.25 MHz, 74.175 MHz, 148.5 MHz, or 148.35 MHz
  • Dual Rate: 148.5 MHz or 148.35 MHz
  • Triple Rate: 148.5 MHz or 148.35 MHz
Note: Not applicable for Intel® Arria® 10, Intel® Cyclone® 10 GX, and Intel® Stratix® 10 devices.
xcvr_refclk_alt

1

Input

Alternative clock input for the Native PHY IP core. The frequency of this signal must be the alternate frequency value of the xcvr_refclk signal.

  • HD-SDI = 74.25 MHz, 74.175 MHz, 148.5 MHz, or 148.35 MHz
  • 3G-SDI = 148.5 MHz or 148.35 MHz
  • HD-SDI Dual Link: 74.25 MHz, 74.175 MHz, 148.5 MHz, or 148.35 MHz
  • Dual Rate: 148.5 MHz or 148.35 MHz
  • Triple Rate: 148.5 MHz or 148.35 MHz
Note: Applicable only when you turn on the Tx PLL Dynamic Switching option. Not applicable for Intel® Arria® 10, Intel® Cyclone® 10 GX, and Intel® Stratix® 10 devices.
tx_clkout

1

Output

TX transceiver parallel output clock.

This frequency for this clock should be the same as the user-provided xcvr_refclk.

Note: Not applicable for Intel® Arria® 10, Intel® Cyclone® 10 GX, and Intel® Stratix® 10 devices.
rx_clkout

1

Output

RX transceiver parallel output clock.
  • SD-SDI = 148.5 MHz
  • HD-SDI = 74.25 MHz or 74.175 MHz, depending on video frame rate
  • 3G-SDI = 148.5 MHz or 148.35 MHz, depending on video frame rate
Note: Not applicable for Intel® Arria® 10, Intel® Cyclone® 10 GX, and Intel® Stratix® 10 devices.
rx_clkout_b

1

Output

RX transceiver parallel output clock for link B. The output clock frequency must be 74.25 or 74.175 MHz, depending on video frame rate.

Note: For HD-SDI dual link only.
Figure 33. TX Clocking Diagram for Intel® Arria® 10, Intel® Cyclone® 10 GX, and Intel® Stratix® 10 Devices


Figure 34. RX Clocking Diagram for Intel® Arria® 10, Intel® Cyclone® 10 GX, and Intel® Stratix® 10 Devices


Note: For a more comprehensive TX and RX Intel® Arria® 10, Intel® Cyclone® 10 GX, and Intel® Stratix® 10 clocking diagrams with transceivers, refer to the respective design example user guides.
Figure 35. TX Clocking Diagram for Arria V, Cyclone V, and Stratix V Devices


Figure 36. RX Clocking Diagram for Arria V, Cyclone V, and Stratix V Devices


Note: For the Arria V, Cyclone V, and Stratix V devices, the source or destination for dual link signals with "_b suffix are the same as the original signals. For example, the destination for rx_clkin_b is the same as rx_clkin. which is directed to the SDI RX protocol block. Similarly, the source of the output signal rx_rst_proto_out_b is the same as rx_rst_proto_out, which comes from the SDI RX PHY management block.

Did you find the information on this page useful?

Characters remaining:

Feedback Message