SDI II Intel® FPGA IP User Guide

ID 683133
Date 10/08/2021
Public

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5.3.21. Remove Sync Bits

The sync bit inserted in 6G-SDI or 12G-SDI data from the source must be removed to allow other receiver submodules to function correctly.

This submodule detects the sync bit presented in the data stream and restores back the correct words, for example TRS words.

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