- Renamed SDI II IP core to Intel FPGA SDI II as per Intel rebranding.
- Changed the term Qsys to Platform Designer
- Added preliminary support for Intel® Stratix® 10 (H-Tile) devices.
- Revised the resource utilization data information for version 17.1.
- Added guidelines on how to change the RX CDR reference clock value for higher clock frequencies.
- Added information about Intel® Stratix® 10 in the Intel FPGA SDI II IP Core Parameters and Intel FPGA SDI II IP Core Signals sections.
- Moved information about the Intel FPGA SDI II design example parameters to the respective design example user guides.
- Rebranded as Intel.
- Revised the resource utilization data and added recommended speed grades information for version 17.0.
- Clarified the description for the tx_trs signal. The first word of both EAV and SAV TRSs could mean two tx_pclk cycles or one tx_pclk cycle depending on the mode selected.
- Added an example of 16-bit rx_format for 6G-SDI and 12G-SDI interfaces.
- Added additional information about the overwrite Payload ID feature.
- Edited the multi-rate (up to 12G-SDI) transmitter and receiver data path block diagrams to include the sync bit insertion and removal blocks.
- Updated the SMPTE standards to the latest naming convention.
- Added a note in the Transceiver Reconfiguration Controller section that the transceiver reconfiguration controller only reconfigures the TX transceiver if you are performing TX clock switching.
- Added detailed description for tx_datain and rx_dataout signals about 6G-SDI and 12G-SDI interfaces.
- Added information about image mapping for 6G-SDI and 12G-SDI interfaces.
- Added information for rx_dataout_valid signal that the 1H4L 1H5L cadence for SD-SDI repeats indefinitely in an ideal case but in a typical scenario the cadence shift periodically (for instance, 1H4L 1H5L 1H5L 1H4L).
- Updated rx_format information to include that for 6G-SDI or 12G-SDI interfaces, each of the 20-bit interface reports its own detected format.
- Added information for pll_powerdown_in signal that sharing Tx PLLs for designs that also implement dynamic reconfiguration require XCVR_TX_PLL_RECONFIG_GROUP QSF assignment.
- Restructured the chapters.
- Added information for the new Design Example parameters.
- Removed all Arria 10 design example related information. For more information about Arria 10 design examples, refer to the SDI II IP Core Design Example User Guide.
- Added clocking diagrams for Arria 10 devices and the V series devices—Arria V, Cyclone V, and Stratix V.
- Added guideline to overcome potential routability issue during Fitter stage.
- Added new option, fPLL, for the Arria 10 TX PLL parameter and removed the ATX PLL option.
- Added estimated run-time settings for the different SDI II video standards.
- Added guideline for transceiver handling. The transceiver handling guidelines differ for Arria 10 devices and the V series devices—Arria V, Cyclone V, and Stratix V.
- Added new transceiver signals:
- Added a new receiver signals: rx_datain and rx_datain_valid.
- Removed these signals: rx_pll_locked and rx_pll_locked_b. These signals are redundant and no longer required after the switch to Native PHY.
- Updated the design example directory.
- Added links to archived versions of the SDI II IP Core User Guide.
- Added information that the rx_format signal for each stream reports its own detected format for 6G-SDI and 12G-SDI interfaces.
- Added information about 3 new interface signals for Arria V, Cyclone V, Stratix V devices: rx_trs_in, pll_powerdown_in, and pll_powerdown_out
- Added reconfiguration management parameters for Arria 10 devices: VIDEO_STANDARD, ED_TXPLL_SWITCH, and XCVR_RCFG_IF_TYPE.
- Added descriptions for the SDI presets available in the Arria 10 Transceiver Native PHY IP core.
- Changed the resource utilization table to include data for each SDI standard and updated the data for version 15.0.
- Added new multi-rate data path block diagrams for transmitter and receiver.
- Added new information about inserting sync bits.
- Renamed the term video payload ID (VPID) to payload ID as per SMPTE specification.
- Renamed Level A to HD-SDI dual link and Level B to 3G-SDI (level B).
- Updated the following new parameter options:
- Added new video standard Multi rate (up to 12G) for Arria 10 devices.
- Added TX PLL reference clock switching option for Dynamic Tx clock switching parameter.
- Added a note for the interface signals to indicate that multi-rate (up to 12G) mode requires 4 streams and the rest require one stream.
- Added a new parameter for Reconfiguration Management: XCVR_TX_PLL_SEL.
- Added information for multi standard support including 6G-SDI and 12G-SDI.
- Added the multi standard (including 6G-SDI and 12G-SDI) information for the following signals:
- Added information that the following signals are not applicable for Arria 10 devices:
- Updated the resource utilization table for version 14.1.
- Changed the names of the following parameters for receiver options:
- Convert Level A to Level B (SMPTE 372M) changed to Convert HD-SDI dual link to 3G-SDI (level B).
- Convert Level B to Level A (SMPTE 372M) changed to Convert 3G-SDI (level B) to HD-SDI dual link.
- Edited information about rx_format signal, which now reports video transport format instead of picture format. The signal reports 3G Level A RGB or YCbCr 4:4:4 format.
- Added support for Arria 10 devices.
- Revised the resource utilization table with information about ALM needed and primary and secondary logic registers.
- Added information related to Arria 10 devices.
- Added new parameters for Example Design Options.
Added new transceiver information—for the Arria 10 devices, the SDI II IP core no longer provides the transceiver, and the TX PLL is no longer wrapped in the transceiver PHY. You must generate the transceiver and the TX PLL separately.
- Added new transceiver signals: rx_ready, gxb_ltr, gxb_ltd, rx_ready_b, gxb_ltr_b, gxb_ltd_b, and trig_rst_ctrl.
- Added information for the newly added Arria 10 design example.
- Added design example entity and simulation testbench diagram.
- Added connecting input signals: rx_manual and rx_is_lockedtodata.
- Added information about transceiver reconfiguration controller— for Arria 10 designs, the reconfiguration interface is integrated into the Arria 10 Native PHY instance and TX PLL.
- Added transceiver reconfiguration controller signals.
- Added information about IP catalog and removed information about MegaWizard Plug-In Manager.
- Added a section for each new feature:
- Tx PLL Dynamic Switching
- SMPTE RP168 Switching
- SD Optional 20-bit Interface for Dual/Triple Rate
- Added information about a new submodule, Convert SD Bits.
- Added information about a new parameter, SD Interface Bit Width.
- Added more information about the design example components—Reconfiguration Management, Reconfiguration Router, Avalon-MM Translators.
- Added more information about the design example operation:
- Transceiver Dynamic Reconfiguration
- Expanding to Multiple Channels
- Updated the protocol and transceiver signals table.
- Updated the resource utilization table.