SDI II Intel® FPGA IP User Guide

ID 683133
Date 10/08/2021
Public

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5.3.10. Detect 1 and 1/1.001 Rates

This submodule indicates if the incoming video stream is running at PAL (1) or NTSC (1/1.001) rate. The output port signal, rx_clkout_is_ntsc_paln is set to 0 if the submodule detects the incoming stream as PAL (148.5 MHz or 74.25 MHz recovered clock) and set to 1 if the incoming stream is detected as NTSC (148.35 MHz or 74.175 MHz recovered clock).

For correct video rate detection, you must set the top level port signal, rx_coreclk_is_ntsc_paln, to the following bit:

  • 0 if the rx_coreclk signal is 297 MHz, 148.5 MHz or the rx_coreclk_hd signal is 74.25 MHz
  • 1 if the rx_coreclk signal is 296.7 MHz, 148.35 MHz or the rx_coreclk_hd signal is 74.175 MHz

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