SDI II Intel® FPGA IP User Guide

ID 683133
Date 10/08/2021

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents Changing RX CDR Reference Clock in Transceiver Native PHY IP Core

For triple-rate or multi-rate modes, you must modify the reference clock value for every profile if you are going to change the CDR reference clock value.

To change the CDR frequency, make the following settings in the respective Transceiver Native PHY parameter editor:

  1. On the RX PMA tab, for the Selected CDR reference clock frequency parameter, select the desired clock frequency, e.g. 297 MHz.
  2. Then, on the Dynamic Reconfiguration tab, click Store configuration to selected profile. The default profile (e.g. 0) is now configured.
  3. If there are more than one profile, select the subsequent profile (e.g. 1) at the Selected reconfiguration profile parameter.
  4. Click Load configuration from selected profile to load profile 1.
  5. Then on the RX PMA tab, select 297 MHz.
  6. Repeat until all the profiles are configured.