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Ixiasoft
Visible to Intel only — GUID: iga1443129335068
Ixiasoft
31.6.1. Stop DMA Operation
The stop DMA operation is also referring to stop dispatcher. Once the “Stop Dispatcher” bit is set in the Control Register, no further new read or write transaction is issued. However, existing transactions pending completion are allowed to complete. The command buffer in both the read host and write host must be clear before the DMA resumes operation via a reset request. Proceed with the following steps for the stop DMA operation:
- Set the Stop Dispatcher bit of the Control Register.
- Recursively check if Stopped bit of Status Register is asserted.
- When the Stopped bit of the Status Register is asserted, reset the DMA by setting the Reset Dispatcher bit of the Control Register. When setting the Reset Dispatcher bit of Control Register, ensures Stop DMA bit remains in set condition.
- Check if the Resetting bit of the Status Register is deasserted. If it is, DMA is now back in normal operation.