Embedded Peripherals IP User Guide

ID 683130
Date 8/15/2023
Public

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Document Table of Contents
1. Introduction 2. Avalon® -ST Multi-Channel Shared Memory FIFO Core 3. Avalon® -ST Single-Clock and Dual-Clock FIFO Cores 4. Avalon® -ST Serial Peripheral Interface Core 5. SPI Core 6. SPI Agent/JTAG to Avalon® Host Bridge Cores 7. Intel eSPI Agent Core 8. eSPI to LPC Bridge Core 9. Ethernet MDIO Core 10. Intel FPGA 16550 Compatible UART Core 11. UART Core 12. JTAG UART Core 13. Intel FPGA Avalon® Mailbox Core 14. Intel FPGA Avalon® Mutex Core 15. Intel FPGA Avalon® I2C (Host) Core 16. Intel FPGA I2C Agent to Avalon® -MM Host Bridge Core 17. Intel FPGA Avalon® Compact Flash Core 18. EPCS/EPCQA Serial Flash Controller Core 19. Intel FPGA Serial Flash Controller Core 20. Intel FPGA Serial Flash Controller II Core 21. Intel FPGA Generic QUAD SPI Controller Core 22. Intel FPGA Generic QUAD SPI Controller II Core 23. Interval Timer Core 24. Intel FPGA Avalon FIFO Memory Core 25. On-Chip Memory (RAM and ROM) Intel FPGA IP 26. On-Chip Memory II (RAM or ROM) Intel FPGA IP 27. Optrex 16207 LCD Controller Core 28. PIO Core 29. PLL Cores 30. DMA Controller Core 31. Modular Scatter-Gather DMA Core 32. Scatter-Gather DMA Controller Core 33. SDRAM Controller Core 34. Tri-State SDRAM Core 35. Video Sync Generator and Pixel Converter Cores 36. Intel FPGA Interrupt Latency Counter Core 37. Performance Counter Unit Core 38. Vectored Interrupt Controller Core 39. Avalon® -ST Data Pattern Generator and Checker Cores 40. Avalon® -ST Test Pattern Generator and Checker Cores 41. System ID Peripheral Core 42. Avalon® Packets to Transactions Converter Core 43. Avalon® -ST Multiplexer and Demultiplexer Cores 44. Avalon® -ST Bytes to Packets and Packets to Bytes Converter Cores 45. Avalon® -ST Delay Core 46. Avalon® -ST Round Robin Scheduler Core 47. Avalon® -ST Splitter Core 48. Avalon® -MM DDR Memory Half Rate Bridge Core 49. Intel FPGA GMII to RGMII Converter Core 50. Intel FPGA MII to RMII Converter Core 51. HPS GMII to TSE 1000BASE-X/SGMII PCS Bridge Core Intel® FPGA IP 52. Intel FPGA HPS EMAC to Multi-rate PHY GMII Adapter Core 53. Intel FPGA MSI to GIC Generator Core 54. Cache Coherency Translator Intel® FPGA IP 55. Lightweight UART Core

22.2. Interface Signals

Table 232.  Interface Signals
Signal Width Direction Description
Clock
clk 1 Input Up to 40 MHz input clock
Reset
reset_n 1 Input Asynchronous reset used to reset QUAD SPI controller
Avalon® memory-mapped interface Agent Interface for CSR (avl_csr)
avl_csr_addr 4 Input Avalon® memory-mapped interface address bus. The address bus is in word addressing.
avl_csr_read 1 Input Avalon® memory-mapped interface read control to csr
avl_csr_write 1 Input Avalon® memory-mapped interface write control to csr
avl_csr_waitrequest 1 Output Avalon® memory-mapped interface waitrequest control from csr
avl_csr_wrdata 32 Input Avalon® memory-mapped interface write data bus to csr
avl_csr_rddata 32 Output Avalon® memory-mapped interface read data bus from csr
avl_csr_rddata_valid 1 Output Avalon® memory-mapped interface read data valid which indicates that csr read data is available
Avalon® memory-mapped interface Agent Interface for Memory Access (avl_ mem)
avl_mem_addr * Input

Avalon® memory-mapped interface address bus. The address bus is in word addressing. The width of the address will depends on the flash memory density minus 2.

If you are using Intel® Arria® 10, then the MSB bits will be used for chip select information. You can select the number of chip select needed in the GUI.

If you select 1 chip select, there will be no extra bit added to avl_mem_addr.

If you select 2 chip selects, there will be one extra bit added to avl_mem_addr.

Chip 1 – b’0

Chip 2 – b’1

If you select 3 chip selects, there will be two extra bit added to avl_mem_addr.

Chip 1 – b’00

Chip 2 – b’01

Chip 3 – b’10

avl_mem_read 1 Input Avalon® memory-mapped interface read control to memory
avl_mem_write 1 Input Avalon® memory-mapped interface write control to memory
avl_mem_wrdata 32 Input Avalon® memory-mapped interface write data bus to memory
avl_mem_byteenble 4 Input Avalon® memory-mapped interface write data enable bit to memory. byteenable bus bit will be always at all high (4’b1111) to support 32-bit data transfer.
avl_mem_burstcount 7 Input Avalon® memory-mapped interface burst count for memory. Value range from 1 to 64
avl_mem_waitrequest 1 Output Avalon® memory-mapped interface waitrequest control from memory
avl_mem_rddata 32 Output Avalon® memory-mapped interface read data bus from memory
avl_mem_rddata_valid 1 Output Avalon® memory-mapped interface read data valid which indicates that memory read data is available
Conduit Interface
flash_dataout 4 Input/Output Input/output port to feed data from flash device
flash_dclk_out 1 Output Provides clock signal to the flash device
flash_ncs 1/3 Output Provides the ncs signal to the flash device
atom_ports_dclk 23 1 Output Provides clock signal to the flash device through ASMI block.
atom_ports_ncs23 1/3 Output Provides the ncs signal to the flash device through ASMI block.
atom_ports_oe23 1 Output Active-low signal to enable dclk and ncs pins to the flash through ASMI block.
atom_ports_dataout23 4 Output Control signal from FPGA design to AS data pin for sending data into the flash through ASMI block.
atom_ports_dataoe23 4 Output Controls AS data pin either as input or output:
  • b’0 – AS data pin as input
  • b’1 – AS data pin as output
atom_ports_datain23 4 Input Signal from AS data pin to FPGA design through ASMI block.
qspi_pins_dclk 24 1 Output Provides clock signal to the flash device.
qspi_pins_ncs24 1/3 Output Provides the ncs signal to the flash device.
qspi_pins_data24 4 Input/Output Input/output port to feed data from flash device.
23 Exported ASMI block signal.
24 Exported SPI pin interface.