Embedded Peripherals IP User Guide

ID 683130
Date 8/15/2023
Public

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Document Table of Contents
1. Introduction 2. Avalon® -ST Multi-Channel Shared Memory FIFO Core 3. Avalon® -ST Single-Clock and Dual-Clock FIFO Cores 4. Avalon® -ST Serial Peripheral Interface Core 5. SPI Core 6. SPI Agent/JTAG to Avalon® Host Bridge Cores 7. Intel eSPI Agent Core 8. eSPI to LPC Bridge Core 9. Ethernet MDIO Core 10. Intel FPGA 16550 Compatible UART Core 11. UART Core 12. JTAG UART Core 13. Intel FPGA Avalon® Mailbox Core 14. Intel FPGA Avalon® Mutex Core 15. Intel FPGA Avalon® I2C (Host) Core 16. Intel FPGA I2C Agent to Avalon® -MM Host Bridge Core 17. Intel FPGA Avalon® Compact Flash Core 18. EPCS/EPCQA Serial Flash Controller Core 19. Intel FPGA Serial Flash Controller Core 20. Intel FPGA Serial Flash Controller II Core 21. Intel FPGA Generic QUAD SPI Controller Core 22. Intel FPGA Generic QUAD SPI Controller II Core 23. Interval Timer Core 24. Intel FPGA Avalon FIFO Memory Core 25. On-Chip Memory (RAM and ROM) Intel FPGA IP 26. On-Chip Memory II (RAM or ROM) Intel FPGA IP 27. Optrex 16207 LCD Controller Core 28. PIO Core 29. PLL Cores 30. DMA Controller Core 31. Modular Scatter-Gather DMA Core 32. Scatter-Gather DMA Controller Core 33. SDRAM Controller Core 34. Tri-State SDRAM Core 35. Video Sync Generator and Pixel Converter Cores 36. Intel FPGA Interrupt Latency Counter Core 37. Performance Counter Unit Core 38. Vectored Interrupt Controller Core 39. Avalon® -ST Data Pattern Generator and Checker Cores 40. Avalon® -ST Test Pattern Generator and Checker Cores 41. System ID Peripheral Core 42. Avalon® Packets to Transactions Converter Core 43. Avalon® -ST Multiplexer and Demultiplexer Cores 44. Avalon® -ST Bytes to Packets and Packets to Bytes Converter Cores 45. Avalon® -ST Delay Core 46. Avalon® -ST Round Robin Scheduler Core 47. Avalon® -ST Splitter Core 48. Avalon® -MM DDR Memory Half Rate Bridge Core 49. Intel FPGA GMII to RGMII Converter Core 50. Intel FPGA MII to RMII Converter Core 51. HPS GMII to TSE 1000BASE-X/SGMII PCS Bridge Core Intel® FPGA IP 52. Intel FPGA HPS EMAC to Multi-rate PHY GMII Adapter Core 53. Intel FPGA MSI to GIC Generator Core 54. Cache Coherency Translator Intel® FPGA IP 55. Lightweight UART Core

8.5. Interface Signals

Table 46.  Interface Signals
Signal Name Width Direction Description
Clock Interface
clk 1 Input Input clock used to clock the IP core.
clk_33 1 Input 33 MHz clock supply to IP core.
Reset Interface
reset_n 1 Input Synchronous reset used to reset the IP core.
LPC Interface to LPC Agent Component
lad[3:0] 4 Input/Output Multiplexed Command, Address, and Data signal.
lframe_n 1 Output Indicates start of a new cycle, or termination of broken cycle.
lreset_n 1 Output Reset signal to LPC agent.
lclk 1 Output 33Mhz clock that drives the LPC agent.
serirq 1 Input/Output Serialized IRQ interrupt signal.
serirq_data_out 13 1 Input/Output Serialized IRQ data signal.
serirq_data_oe 13 1 Input/Output Serialized IRQ data output enable signal.
serirq_data_in 13 1 Input/Output Serialized IRQ data signal.
lad_out[3:0] 13 4 Output Multiplexed command, address and data signal
lad_oe 13 1 Output Data signal output enable
lad_in[3:0] 13 4 Input Multiplexed command, address and data signal
Avalon Interface
avmm_write 1 Input Avalon write control signal for register access.
avmm_read 1 Input Avalon read control signal for register access.
avmm_writedata[31:0] 32 Input Avalon write data bus for register access.
avmm_address[4:0] 5 Input Avalon address bus for register access.
avmm_readdata[31:0] 32 Output Avalon read data bus for register access.
eSPI Interface
espi_clk 1 Input eSPI serial clock. Frequency range from 20Mhz to 66Mhz.
espi_reset_n 1 Input eSPI reset. Assertion of this reset signal does not reset the channel’s FIFO.
espi_cs_n 1 Input eSPI chip select.
espi_data[1:0]/[3:0] 2/4 Input/Output eSPI bidirectional data bus. Data bus lane depending on parameter IO_MODE.
espi_alert_n 1 Output eSPI alert.
Conduit Ports
slp_s5_n 1 Output Server platform related signal.
slp_s4_n 1 Output
slp_s3_n 1 Output
slp_a_n 1 Output
slp_lan_n 1 Output
slp_wlan_n 1 Output
sus_stat_n 1 Output
sus_pwrdn_ack 1 Output
sus_warn_n 1 Output
pch_to_ec[7:0] 8 Output
oob_rst_warn 1 Output
host_rst_warn 1 Output
smiout_n 1 Output
nmiout_n 1 Output
host_c10 1 Output
pltrst_n 1 Output
ec_to_pch [7:0] 8 Input
sus_ack_n 1 Input
slave_boot_load_done 1 Input
slave_boot_load_status 1 Input
oob_rst_ack 1 Input
wake_n 1 Input
pme_n 1 Input
sci_n 1 Input
rcin_n 1 Input
host_rst_ack 1 Input
rsmrst_n 1 Input
13 This signal is only available when you turn on the parameter: Enable tri-state control ports on LPC data bus and Serial IRQ line.