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29.1. Core Overview
The PLL core is scheduled for product obsolescence and discontinued support. Therefore, Intel recommends that you use the Avalon® ALTPLL core in your designs.
The core takes an Platform Designer system clock as its input and generates PLL output clocks locked to that reference clock.
The PLL cores support the following features:
- All PLL features provided by Intel FPGA ALTPLL IP core. The exact feature set depends on the device family.
- Access to status and control signals via Avalon® Memory-Mapped ( Avalon® -MM) registers or top-level signals on the Platform Designer system module.
- Dynamic phase reconfiguration in Stratix® III and Stratix® IV device families.
The PLL output clocks are made available in two ways:
- As sources to system-wide clocks in your Platform Designer system.
- As output signals on your Platform Designer system module.
For details about the ALTPLL IP core, refer to the ALTPLL IP Core User Guide.