A newer version of this document is available. Customers should click here to go to the newest version.
Visible to Intel only — GUID: rqb1488476853250
Ixiasoft
Visible to Intel only — GUID: rqb1488476853250
Ixiasoft
25.2.1. Memory Type
This options defines the structure of the on-chip memory:
- RAM (writable)—This setting creates a readable and writable memory.
- ROM (read only)—This setting creates a read-only memory.
- Dual-port access—This setting creates a memory component with two agents, which allows two hosts to access the memory simultaneously.
Note: The memory component operates under true dual-port mode where both agent ports have address ports for read or write operations. If two hosts access the same address simultaneously in a dual-port memory undefined results will occur. Concurrent accesses are only a problem for two writes. A read and write to the same location will read out the old data and store the new data.
- Single clock operation—Single clock operation setting creates single clock source to clock both agents port. If single clock operation is not selected, each of the two agents port is clocked by different clock sources.
Note: For Intel® Stratix® 10 devices, only single clock operation is supported.
- Read During Write Mode—This setting determines what the output data of the memory should be when a simultaneous read and write to the same memory location occurs.
- Block type—This setting directs the Intel® Quartus® Prime software to use a specific type of memory block when fitting the on-chip memory in the FPGA.
Note: The MRAM blocks do not allow the contents to be initialized during power up. The M512s memory type does not support dual-port mode where both ports support both reads and writes.
Because of the constraints on some memory types, it is frequently best to use the Auto setting. Auto allows the Intel® Quartus® Prime software to choose a type and the other settings direct the Intel® Quartus® Prime software to select a particular type.