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Visible to Intel only — GUID: iga1405469081936
Ixiasoft
Visible to Intel only — GUID: iga1405469081936
Ixiasoft
11.4.3.4. control Register
The control register consists of individual bits, each controlling an aspect of the UART core's operation. The value in the control register can be read at any time.
Each bit in the control register enables an IRQ for a corresponding bit in the status register. When both a status bit and its corresponding interrupt-enable bit are 1, the core generates an IRQ.
Bit | Name | Access | Description |
---|---|---|---|
0 | IPE | RW | Enable interrupt for a parity error. |
1 | IFE | RW | Enable interrupt for a framing error. |
2 | IBRK | RW | Enable interrupt for a break detect. |
3 | IROE | RW | Enable interrupt for a receiver overrun error. |
4 | ITOE | RW | Enable interrupt for a transmitter overrun error. |
5 | ITMT | RW | Enable interrupt for a transmitter shift register empty. |
6 | ITRDY | RW | Enable interrupt for a transmission ready. |
7 | IRRDY | RW | Enable interrupt for a read ready. |
8 | IE | RW | Enable interrupt for an exception. |
9 | TRBK | RW | Transmit break. The TRBK bit allows an Avalon® -MM host peripheral to transmit a break character over the TXD output. The TXD signal is forced to 0 when the TRBK bit is set to 1. The TRBK bit overrides any logic level that the transmitter logic would otherwise drive on the TXD output. The TRBK bit interferes with any transmission in process. The Avalon® -MM host peripheral must set the TRBK bit back to 0 after an appropriate break period elapses. |
1020 | IDCTS | RW | Enable interrupt for a change in CTS signal. |
11 20 | RTS | RW | Request to send (RTS) signal. The RTS bit directly feeds the RTS_N output. An Avalon® -MM host peripheral can write the RTS bit at any time. The value of the RTS bit only affects the RTS_N output; it has no effect on the transmitter or receiver logic. Because the RTS_N output is logic negative, when the RTS bit is 1, a low logic-level (0) is driven on the RTS_N output. |
1220 | IEOP | RW | Enable interrupt for end-of-packet condition. |