Embedded Peripherals IP User Guide

ID 683130
Date 8/15/2023
Public

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Document Table of Contents
1. Introduction 2. Avalon® -ST Multi-Channel Shared Memory FIFO Core 3. Avalon® -ST Single-Clock and Dual-Clock FIFO Cores 4. Avalon® -ST Serial Peripheral Interface Core 5. SPI Core 6. SPI Agent/JTAG to Avalon® Host Bridge Cores 7. Intel eSPI Agent Core 8. eSPI to LPC Bridge Core 9. Ethernet MDIO Core 10. Intel FPGA 16550 Compatible UART Core 11. UART Core 12. JTAG UART Core 13. Intel FPGA Avalon® Mailbox Core 14. Intel FPGA Avalon® Mutex Core 15. Intel FPGA Avalon® I2C (Host) Core 16. Intel FPGA I2C Agent to Avalon® -MM Host Bridge Core 17. Intel FPGA Avalon® Compact Flash Core 18. EPCS/EPCQA Serial Flash Controller Core 19. Intel FPGA Serial Flash Controller Core 20. Intel FPGA Serial Flash Controller II Core 21. Intel FPGA Generic QUAD SPI Controller Core 22. Intel FPGA Generic QUAD SPI Controller II Core 23. Interval Timer Core 24. Intel FPGA Avalon FIFO Memory Core 25. On-Chip Memory (RAM and ROM) Intel FPGA IP 26. On-Chip Memory II (RAM or ROM) Intel FPGA IP 27. Optrex 16207 LCD Controller Core 28. PIO Core 29. PLL Cores 30. DMA Controller Core 31. Modular Scatter-Gather DMA Core 32. Scatter-Gather DMA Controller Core 33. SDRAM Controller Core 34. Tri-State SDRAM Core 35. Video Sync Generator and Pixel Converter Cores 36. Intel FPGA Interrupt Latency Counter Core 37. Performance Counter Unit Core 38. Vectored Interrupt Controller Core 39. Avalon® -ST Data Pattern Generator and Checker Cores 40. Avalon® -ST Test Pattern Generator and Checker Cores 41. System ID Peripheral Core 42. Avalon® Packets to Transactions Converter Core 43. Avalon® -ST Multiplexer and Demultiplexer Cores 44. Avalon® -ST Bytes to Packets and Packets to Bytes Converter Cores 45. Avalon® -ST Delay Core 46. Avalon® -ST Round Robin Scheduler Core 47. Avalon® -ST Splitter Core 48. Avalon® -MM DDR Memory Half Rate Bridge Core 49. Intel FPGA GMII to RGMII Converter Core 50. Intel FPGA MII to RMII Converter Core 51. HPS GMII to TSE 1000BASE-X/SGMII PCS Bridge Core Intel® FPGA IP 52. Intel FPGA HPS EMAC to Multi-rate PHY GMII Adapter Core 53. Intel FPGA MSI to GIC Generator Core 54. Cache Coherency Translator Intel® FPGA IP 55. Lightweight UART Core

7.4. Interface Signals

Table 29.  Interface Signals
Signal Names Width (bit) Direction Description
Clock Interface
clk 1 Input Input clock signal.
Reset Interface
reset_n 1 Input Synchronous reset signal.
Avalon® memory-mapped interface Agent Interface 6
avmm_read 1 Input Use this signal to enable read from the status register, error register, posted RX fifo or non-posted RX fifo.
avmm_readdata[31:0] 32 Output Use this signal to read data from the status register , error register, posted RX fifo or non-posted RX fifo.
avmm_write 1 Input Use this signal to enable write to posted TX fifo or non-posted TX fifo.
avmm_writedata[31:0] 32 Input Use this signal to write data to posted TX fifo or non-posted TX fifo.
avmm_address[4:0] 5 Input Avalon address determines address to access the respective register/fifo.
Interrupt Signal
irq 1 Output Interrupt signal reflects update to status register. It is also triggered when the error register bit is asserted.
eSPI Interface
espi_clk 1 Input eSPI serial clock signal.

Frequency range: 20 MHz to 66 MHz.

espi_reset_n 1 Input eSPI reset signal.
espi_cs_n 1 Input eSPI chip select signal.
espi_data[1:0]/[3:0] 2 or 4 Input/Output eSPI bidirectional data bus. Data bus configuration is determined by the eSPI Mode of Operation parameter.
  • 2-bit data bus:
    • Single I/O
    • Single and Dual I/O
  • 4-bit data bus:
    • Single and Quad I/O
    • Single, Dual, and Quad I/O
espi_alert_n 1 Output eSPI alert signal.
Conduit
slp_s5_n 1 Output S5 sleep control signal is sent when the power to non-critical systems should be shut off in S5.
slp_s4_n 1 Output S4 sleep control signal is sent when the power to non-critical systems should be shut off in S4.
slp_s3_n 1 Output S3 sleep control signal is sent when the power to non-critical systems should be shut off in S3.
slp_a_n 1 Output Use sleep A signal to support ASW devices that need power in the SX platform when the Intel® ME is on.
slp_lan_n 1 Output LAN sub-system sleep control signal is sent when the power to external wired LAN PHY can be shut off.
slp_wlan_n 1 Output Wireless LAN sub-system sleep control signal is sent when the power to external wireless LAN PHY can be shut off.
sus_stat_n 1 Output Suspend status signal is sent when the system is about to enter a low power state.
sus_pwrdn_ack 1 Output Suspend power down acknowledgement signal.
sus_warn_n 1 Output Suspend warning signal.
oob_rst_warn 1 Output Host sends this signal before the OOB processor is about to reset.
host_rst_warn 1 Output Host sends this signal before the host is about to reset.
smiout_n 1 Output Host sends this signal indicating the occurrence of SMI event.
nmiout_n 1 Output Host sends this signal indicating the occurrence of NMI event.
host_c10 1 Output Indicates that the host CPU has entered deep power down state C10 or deeper.
pch_to_ec[7:0] 8 Output 8 independent Virtual Wire placeholder from the platform controller hub (eSPI host) to the eSPI agent IP.
ec_to_pch[7:0] 8 Input 8 independent Virtual Wire placeholder from eSPI agent IP to the platform controller hub (eSPI host).
sus_ack_n 1 Input Suspend acknowledgement signal.
oob_rst_ack 1 Input OOB reset acknowledgement signal.
wake_n 1 Input This signal wakes host up from Sx on any event. It can also wake up on LID switch or AC insertion event.
pme_n 1 Input This signal wakes host up from Sx through PCI defined PME.
sci_n 1 Input General purpose alert signal which results in OS invoking ACPI method.
smi_n 1 Input General purpose alert signal which results in BIOS invoking SMI code.
rcin_n 1 Input To request CPU reset on behalf of the keyboard controller.
host_rst_ack 1 Input Host reset acknowledgement signal.
slave_boot_load_done 1 Input Indicates boot load completion.
slave_boot_load_status 1 Input Indicates boot load status.
pc_port<n>_<direction>[(m-1):0] m = 8/16/32 Input/Output Peripheral channel I/O ports with configurable data width and direction.

n = configurable value from 00 to A0.

For example: pc_port80_out[15:0]

rsmrst_n 1 Input This signal provides input reset to some of the Virtual Wire indexes.
vw_irq0 [7:0] 7 8 Input The virtual interrupt signal is triggered by an external source to enable communication with eSPI core.
vw_irq1 [7:0]7 8 Input
pltrst_n 1 Output Platform Reset Signal.
6 Use Avalon® memory-mapped interface to access the status register with Avalon address set to 00h and also the FIFO in the PC channel with Avalon address set to 04h.
7 The eSPI client can send multiple VW IRQ index groups in a single eSPI packet, up to the Operating Maximum VW Count programmed in its Virtual Wire Capabilities and Configuration Channel. For more information, refer to Table 9: Virtual Wire Index in the Enhanced Serial Peripheral Interface (eSPI) Base Specification.