Embedded Peripherals IP User Guide

ID 683130
Date 8/15/2023
Public

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Document Table of Contents
1. Introduction 2. Avalon® -ST Multi-Channel Shared Memory FIFO Core 3. Avalon® -ST Single-Clock and Dual-Clock FIFO Cores 4. Avalon® -ST Serial Peripheral Interface Core 5. SPI Core 6. SPI Agent/JTAG to Avalon® Host Bridge Cores 7. Intel eSPI Agent Core 8. eSPI to LPC Bridge Core 9. Ethernet MDIO Core 10. Intel FPGA 16550 Compatible UART Core 11. UART Core 12. JTAG UART Core 13. Intel FPGA Avalon® Mailbox Core 14. Intel FPGA Avalon® Mutex Core 15. Intel FPGA Avalon® I2C (Host) Core 16. Intel FPGA I2C Agent to Avalon® -MM Host Bridge Core 17. Intel FPGA Avalon® Compact Flash Core 18. EPCS/EPCQA Serial Flash Controller Core 19. Intel FPGA Serial Flash Controller Core 20. Intel FPGA Serial Flash Controller II Core 21. Intel FPGA Generic QUAD SPI Controller Core 22. Intel FPGA Generic QUAD SPI Controller II Core 23. Interval Timer Core 24. Intel FPGA Avalon FIFO Memory Core 25. On-Chip Memory (RAM and ROM) Intel FPGA IP 26. On-Chip Memory II (RAM or ROM) Intel FPGA IP 27. Optrex 16207 LCD Controller Core 28. PIO Core 29. PLL Cores 30. DMA Controller Core 31. Modular Scatter-Gather DMA Core 32. Scatter-Gather DMA Controller Core 33. SDRAM Controller Core 34. Tri-State SDRAM Core 35. Video Sync Generator and Pixel Converter Cores 36. Intel FPGA Interrupt Latency Counter Core 37. Performance Counter Unit Core 38. Vectored Interrupt Controller Core 39. Avalon® -ST Data Pattern Generator and Checker Cores 40. Avalon® -ST Test Pattern Generator and Checker Cores 41. System ID Peripheral Core 42. Avalon® Packets to Transactions Converter Core 43. Avalon® -ST Multiplexer and Demultiplexer Cores 44. Avalon® -ST Bytes to Packets and Packets to Bytes Converter Cores 45. Avalon® -ST Delay Core 46. Avalon® -ST Round Robin Scheduler Core 47. Avalon® -ST Splitter Core 48. Avalon® -MM DDR Memory Half Rate Bridge Core 49. Intel FPGA GMII to RGMII Converter Core 50. Intel FPGA MII to RMII Converter Core 51. HPS GMII to TSE 1000BASE-X/SGMII PCS Bridge Core Intel® FPGA IP 52. Intel FPGA HPS EMAC to Multi-rate PHY GMII Adapter Core 53. Intel FPGA MSI to GIC Generator Core 54. Cache Coherency Translator Intel® FPGA IP 55. Lightweight UART Core

40.6.3. Register Maps

This section describes the register maps for the test pattern generator and checker cores.

Test Pattern Generator Control and Status Registers

The table below shows the offset for the test pattern generator control and status registers. Each register is 32 bits wide.

Table 429.  Test Pattern Generator Control and Status Register Map
Offset Register Name
base + 0 status
base + 1 control
base + 2 fill
Table 430.  Status Field Descriptions
Bit(s) Name Access Description
[15:0] ID RO A constant value of 0x64.
[23:16] NUMCHANNELS RO The configured number of channels.
[30:24] NUMSYMBOLS RO The configured number of symbols per beat.
[31] SUPPORTPACKETS RO A value of 1 indicates packet support.
Table 431.  Control Field Descriptions
Bit(s) Name Access Description
[0] ENABLE RW Setting this bit to 1 enables the test pattern generator core.
[7:1] Reserved
[16:8] THROTTLE RW Specifies the throttle value which can be between 0–256, inclusively. This value is used in conjunction with a pseudorandom number generator to throttle the data generation rate.

Setting THROTTLE to 0 stops the test pattern generator core. Setting it to 256 causes the test pattern generator core to run at full throttle. Values between 0–256 result in a data rate proportional to the throttle value.

[17] SOFT RESET RW When this bit is set to 1, all internal counters and statistics are reset. Write 0 to this bit to exit reset.
[31:18] Reserved
Table 432.  Fill Field Descriptions
Bit(s) Name Access Description
[0] BUSY RO A value of 1 indicates that data transmission is in progress, or that there is at least one command in the command queue.
[6:1] Reserved
[15:7] FILL RO The number of commands currently in the command FIFO.
[31:16] Reserved

Test Pattern Generator Command Registers

The table below shows the offset for the command registers. Each register is 32 bits wide.

Table 433.  Test Pattern Command Register Map
Offset Register Name
base + 0 cmd_lo
base + 1 cmd_hi

The command is pushed into the FIFO only when the cmd_lo register is written to.

Table 434.  cmd_lo Field Descriptions
Bit(s) Name Access Description
[15:0] SIZE RW The segment size in symbols. Except for the last segment in a packet, the size of all segments must be a multiple of the configured number of symbols per beat. If this condition is not met, the test pattern generator core inserts additional symbols to the segment to ensure the condition is fulfilled.
[29:16] CHANNEL RW The channel to send the segment on. If the channel signal is less than 14 bits wide, the low order bits of this register are used to drive the signal.
[30] SOP RW Set this bit to 1 when sending the first segment in a packet. This bit is ignored when packets are not supported.
[31] EOP RW Set this bit to 1 when sending the last segment in a packet. This bit is ignored when packets are not supported.
Table 435.  cmd_hi Field Descriptions
Bit(s) Name Access Description
[15:0] SIGNALLED ERROR RW Specifies the value to drive the error signal. A non-zero value creates a signalled error.
[23:16] DATA ERROR RW The output data is XORed with the contents of this register to create data errors. To stop creating data errors, set this register to 0.
[24] SUPRESS SOP RW Set this bit to 1 to suppress the assertion of the startofpacket signal when the first segment in a packet is sent.
[25] SUPRESS EOP RW Set this bit to 1 to suppress the assertion of the endofpacket signal when the last segment in a packet is sent.

Test Pattern Checker Control and Status Registers

The table below shows the offset for the control and status registers. Each register is 32 bits wide.

Table 436.  Test Pattern Checker Control and Status Register Map
Offset Register Name
base + 0 status
base + 1 control
base + 2 Reserved
base + 3
base + 4
base + 5 exception_descriptor
base + 6 indirect_select
base + 7 indirect_count
Table 437.  Status Field Descriptions
Bit(s) Name Access Description
[15:0] ID RO Contains a constant value of 0x65.
[23:16] NUMCHANNELS RO The configured number of channels.
[30:24] NUMSYMBOLS RO The configured number of symbols per beat.
[31] SUPPORTPACKETS RO A value of 1 indicates packet support.
Table 438.  Control Field Descriptions
Bit(s) Name Access Description
[0] ENABLE RW Setting this bit to 1 enables the test pattern checker.
[7:1] Reserved
[16:8] THROTTLE RW Specifies the throttle value which can be between 0–256, inclusively. This value is used in conjunction with a pseudorandom number generator to throttle the data generation rate.

Setting THROTTLE to 0 stops the test pattern generator core. Setting it to 256 causes the test pattern generator core to run at full throttle. Values between 0–256 result in a data rate proportional to the throttle value.

[17] SOFT RESET RW When this bit is set to 1, all internal counters and statistics are reset. Write 0 to this bit to exit reset.
[31:18] Reserved

The table below describes the exception_descriptor register bits. If there is no exception, reading this register returns 0.

Table 439.  exception_descriptor Field Descriptions
Bit(s) Name Access Description
[0] DATA ERROR RO A value of 1 indicates that an error is detected in the incoming data.
[1] MISSINGSOP RO A value of 1 indicates missing start-of-packet.
[2] MISSINGEOP RO A value of 1 indicates missing end-of-packet.
[7:3] Reserved
[15:8] SIGNALLED ERROR RO The value of the error signal.
[23:16] Reserved
[31:24] CHANNEL RO The channel on which the exception was detected.
Table 440.  indirect_select Field Descriptions
Bit Bits Name Access Description
[7:0] INDIRECT CHANNEL RW Specifies the channel number that applies to the INDIRECT PACKET COUNT, INDIRECT SYMBOL COUNT, and INDIRECT ERROR COUNT registers.
[15:8] Reserved
[31:16] INDIRECT ERROR RO The number of data errors that occurred on the channel specified by INDIRECT CHANNEL.
Table 441.  indirect_count Field Descriptions
Bit Bits Name Access Description
[15:0] INDIRECT PACKET COUNT RO The number of packets received on the channel specified by INDIRECT CHANNEL.
[31:16] INDIRECT SYMBOL COUNT RO The number of symbols received on the channel specified by INDIRECT CHANNEL.