1.3.2. Inferring Multiply-Accumulator and Multiply-Adder Functions
A simple multiply-accumulator consists of a multiplier feeding an addition operator. The addition operator feeds a set of registers that then feeds the second input to the addition operator. A simple multiply-adder consists of two to four multipliers feeding one or two levels of addition, subtraction, or addition/subtraction operators. Addition is always the second-level operator, if it is used. In addition to the multiply-accumulator and multiply-adder, the Intel® Quartus® Prime Fitter also places input and output registers into the DSP blocks to pack registers and improve performance and area utilization.
Some device families offer additional advanced multiply-adder and accumulator functions, such as complex multiplication, input shift register, or larger multiplications.
Verilog HDL Multiply-Accumulator
module sum_of_four_multiply_accumulate #(parameter INPUT_WIDTH=18, parameter OUTPUT_WIDTH=44) ( input clk, ena, input [INPUT_WIDTH-1:0] dataa, datab, datac, datad, input [INPUT_WIDTH-1:0] datae, dataf, datag, datah, output reg [OUTPUT_WIDTH-1:0] dataout ); // Each product can be up to 2*INPUT_WIDTH bits wide. // The sum of four of these products can be up to 2 bits wider. wire [2*INPUT_WIDTH+1:0] mult_sum; // Store the results of the operations on the current inputs assign mult_sum = (dataa * datab + datac * datad) + (datae * dataf + datag * datah); // Store the value of the accumulation always @ (posedge clk) begin if (ena == 1) begin dataout <= dataout + mult_sum; end end endmodule
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