Intel® Quartus® Prime Pro Edition User Guide: Design Recommendations

ID 683082
Date 9/26/2022
Public
Document Table of Contents

2.5.5.6. Design Assistant Tags

Different Design Assistant Tags apply to each rule to extend search or filter capabilities based on the following facets of the rule. Refer to the Design Assistant Rule Settings to view which tags apply to each rule.
Table 6.  Design Assistant Tags

Tag

Description

cdc-bus Design rule checks related to topologies that use a bus to transfer multiple bits of data between clock domains at once.
clock-skew Design rule checks related to clock skew.
design-partition Design rule checks which check design partitions.
dsp Design rule checks related to DSP blocks inside the FPGA fabric.
false-positive-synchronizer Design rule checks related to automatically-detected synchronizer chains that may have been over-zealously detected.
global-signal Design rule checks related to global signals.
impossible-requirements Design rule checks which check the requirements on failing timing paths and flag those which fail by construction.
ip-parameterization Design rule checks which look for parameterizable IP modules which may need to be adjusted to meet performance specifications.
intrinsic-margin Design rule checks which use the Intrinsic Margin metric (slack ignoring cell delay, IC delay and clock skew) to diagnose potential timing issues on failing paths.
latch Design rule checks related to latches.
logic-levels Design rule checks which flag potentially problematic amounts of logic on a timing path.
minimum-pulse-width Design rule checks related to minimum pulse width.
nonstandard-timing Design rule checks related to topologies which have unique timing analysis methodologies and may prove problematic.
partial-reconfiguration Design rule checks which check Partial Reconfiguration designs.
place Design rule checks which pertain to the Compiler's Place stage.
project-settings Design rule checks related to validating the project settings.
ram Design rule checks related to M20k blocks inside the FPGA fabric.
region-constraints Design rule checks related to region constraints in the design (both placement and routing).
register-duplication Design rule checks related to duplication of registers in the design, either manually or automatically.
register-spread Design rule checks related to measuring the spread of a register's sinks, as found in the "Report Register Spread" command.
reset-usage Design rule checks related to safe resets or appropriate use of reset modes.
reset-reachability Design rule checks related to reachability analysis of reset signals, including convergence of multiple reset signals.
resource-usage Design rule checks related to managing the resource usage of the design.
retime Design rule checks which pertain to the Compiler's Retime stage.
route Design rule checks which pertain to the Compiler's Route stage.
sdc Design rule checks related to SDC validity checking.
synchronizer Design rule checks related to synchronizer chains.
synthesis Design rule checks which pertain to the Compiler's Analysis & Synthesis stage.
system Design rule checks which validate full-system design.

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