1.1. Using Provided HDL Templates 1.2. Instantiating IP Cores in HDL 1.3. Inferring Multipliers and DSP Functions 1.4. Inferring Memory Functions from HDL Code 1.5. Register and Latch Coding Guidelines 1.6. General Coding Guidelines 1.7. Designing with Low-Level Primitives 1.8. Cross-Module Referencing (XMR) in HDL Code 1.9. Using force Statements in HDL Code 1.10. Recommended HDL Coding Styles Revision History
126.96.36.199. Use Synchronous Memory Blocks 188.8.131.52. Avoid Unsupported Reset and Control Conditions 184.108.40.206. Check Read-During-Write Behavior 220.127.116.11. Controlling RAM Inference and Implementation 18.104.22.168. Single-Clock Synchronous RAM with Old Data Read-During-Write Behavior 22.214.171.124. Single-Clock Synchronous RAM with New Data Read-During-Write Behavior 126.96.36.199. Simple Dual-Port, Dual-Clock Synchronous RAM 188.8.131.52. True Dual-Port Synchronous RAM 184.108.40.206. Mixed-Width Dual-Port RAM 220.127.116.11. RAM with Byte-Enable Signals 18.104.22.168. Specifying Initial Memory Contents at Power-Up
22.214.171.124. If Performance is Important, Optimize for Speed 126.96.36.199. Use Separate CRC Blocks Instead of Cascaded Stages 188.8.131.52. Use Separate CRC Blocks Instead of Allowing Blocks to Merge 184.108.40.206. Take Advantage of Latency if Available 220.127.116.11. Save Power by Disabling CRC Blocks When Not in Use 18.104.22.168. Initialize the Device with the Synchronous Load (sload) Signal
3.4.1. Apply Complete System-Centric Timing Constraints for the Timing Analyzer 3.4.2. Force the Identification of Synchronization Registers 3.4.3. Set the Synchronizer Data Toggle Rate 3.4.4. Optimize Metastability During Fitting 3.4.5. Increase the Length of Synchronizers to Protect and Optimize 3.4.6. Increase the Number of Stages Used in Synchronizers 3.4.7. Select a Faster Speed Grade Device
2.1. Following Synchronous FPGA Design Practices
The first step in good design methodology is to understand the implications of your design practices and techniques. This section outlines the benefits of optimal synchronous design practices and the hazards involved in other approaches.
Good synchronous design practices can help you meet your design goals consistently. Problems with other design techniques can include reliance on propagation delays in a device, which can lead to race conditions, incomplete timing analysis, and possible glitches.
In a synchronous design, a clock signal triggers every event. If you ensure that all the timing requirements of the registers are met, a synchronous design behaves in a predictable and reliable manner for all process, voltage, and temperature (PVT) conditions. You can easily migrate synchronous designs to different device families or speed grades.
Implementing Synchronous Designs
Asynchronous Design Hazards
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