ID 683082
Date 9/26/2022
Public

1.6.4.2. Verilog HDL State Machines

To ensure proper recognition and inference of Verilog HDL state machines, observe the following additional Verilog HDL guidelines.

Refer to your synthesis tool documentation for specific coding recommendations. If the synthesis tool doesn't recognize and infer the state machine, the tool implements the state machine as regular logic gates and registers, and the state machine doesn't appear as a state machine in the Analysis & Synthesis section of the Intel® Quartus® Prime Compilation Report. In this case, Intel® Quartus® Prime synthesis does not perform any optimizations specific to state machines.

• If you are using the SystemVerilog standard, use enumerated types to describe state machines.
• Represent the states in a state machine with the parameter data types in Verilog-1995 and Verilog-2001, and use the parameters to make state assignments. This parameter implementation makes the state machine easier to read and reduces the risk of errors during coding.
• Do not directly use integer values for state variables, such as next_state <= 0. However, using an integer does not prevent inference in the Intel® Quartus® Prime software.
• Intel® Quartus® Prime software doesn't infer a state machine if the state transition logic uses arithmetic similar to the following example:
case (state)
0: begin
if (ena) next_state <= state + 2;
else next_state <= state + 1;
end
1: begin
...
endcase
• Intel® Quartus® Prime software doesn't infer a state machine if the state variable is an output.
• Intel® Quartus® Prime software doesn't infer a state machine for signed variables.