1.1. Using Provided HDL Templates 1.2. Instantiating IP Cores in HDL 1.3. Inferring Multipliers and DSP Functions 1.4. Inferring Memory Functions from HDL Code 1.5. Register and Latch Coding Guidelines 1.6. General Coding Guidelines 1.7. Designing with Low-Level Primitives 1.8. Cross-Module Referencing (XMR) in HDL Code 1.9. Using force Statements in HDL Code 1.10. Recommended HDL Coding Styles Revision History
188.8.131.52. Use Synchronous Memory Blocks 184.108.40.206. Avoid Unsupported Reset and Control Conditions 220.127.116.11. Check Read-During-Write Behavior 18.104.22.168. Controlling RAM Inference and Implementation 22.214.171.124. Single-Clock Synchronous RAM with Old Data Read-During-Write Behavior 126.96.36.199. Single-Clock Synchronous RAM with New Data Read-During-Write Behavior 188.8.131.52. Simple Dual-Port, Dual-Clock Synchronous RAM 184.108.40.206. True Dual-Port Synchronous RAM 220.127.116.11. Mixed-Width Dual-Port RAM 18.104.22.168. RAM with Byte-Enable Signals 22.214.171.124. Specifying Initial Memory Contents at Power-Up
126.96.36.199. If Performance is Important, Optimize for Speed 188.8.131.52. Use Separate CRC Blocks Instead of Cascaded Stages 184.108.40.206. Use Separate CRC Blocks Instead of Allowing Blocks to Merge 220.127.116.11. Take Advantage of Latency if Available 18.104.22.168. Save Power by Disabling CRC Blocks When Not in Use 22.214.171.124. Initialize the Device with the Synchronous Load (sload) Signal
3.4.1. Apply Complete System-Centric Timing Constraints for the Timing Analyzer 3.4.2. Force the Identification of Synchronization Registers 3.4.3. Set the Synchronizer Data Toggle Rate 3.4.4. Optimize Metastability During Fitting 3.4.5. Increase the Length of Synchronizers to Protect and Optimize 3.4.6. Increase the Number of Stages Used in Synchronizers 3.4.7. Select a Faster Speed Grade Device
1.7. Designing with Low-Level Primitives
Low-level HDL design is the practice of using low-level primitives and assignments to dictate a particular hardware implementation for a piece of logic. Low-level primitives are small architectural building blocks that assist you in creating your design.
With the Intel® Quartus® Prime software, you can use low-level HDL design techniques to force a specific hardware implementation that can help you achieve better resource utilization or faster timing results.
Note: Using low-level primitives is an optional advanced technique to help with specific design challenges. For many designs, synthesizing generic HDL source code and Intel FPGA IP cores give you the best results.
Low-level primitives allow you to use the following types of coding techniques:
- Instantiate the logic cell or LCELL primitive to prevent Intel® Quartus® Prime Pro Edition synthesis from performing optimizations across a logic cell
- Instantiate registers with specific control signals using DFF primitives
- Specify the creation of LUT functions by identifying the LUT boundaries
- Use I/O buffers to specify I/O standards, current strengths, and other I/O assignments
- Use I/O buffers to specify differential pin names in your HDL code, instead of using the automatically-generated negative pin name for each pair
For details about and examples of using these types of assignments, refer to the Designing with Low-Level Primitives User Guide.
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