Intel® Quartus® Prime Pro Edition User Guide: Design Recommendations

ID 683082
Date 9/26/2022
Public

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1.9. Using force Statements in HDL Code

force statement in SystemVerilog is a continuous procedural assignment on a net or a variable.
Applying a force statement to a net or variable overrides all other drivers to that net or variable. In simulation, you can use a force statement in conjunction with a release statement. However, Intel® Quartus® Prime software synthesis supports using only the force statement to override the drivers of a net (gate outputs, module outputs, and continuous assignments) and previous assignments made on a particular net or a net bus.
Note: Synthesis supports using a force statement only inside an initial block.

Examples of force Statements in Synthesis

The following are some examples of force statements that the Intel® Quartus® Prime software synthesis supports:

Using a force Statement to Set Counter enable to 0

The following is an example of how you can use a force statement to tie the en port of the counter instance u1 to logic 0:

module top(clk, rst. enable, dout);
  input clk, rst, enable;
  output [3:0] dout;
  counter u1(.clk(clk), .reset(rst), .en(enable), .q(dout));

  initial  begin
    force u1.en = 1’b0;
  end
endmodule

You can observe that the force statement overrides the other driver of the en port, which is the enable port of the top module.

Using a force Statement to Change Connections

The following example shows how you can use a force statement to change the connections in the design:

module top(input [3:0] din, din1, output logic [3:0] dout, dout1, input clk, rst);
  dff i0(.din(din), .dout(dout), .clk(clk), .rst(rst) );
  dff i1(.din(din1), .dout(dout1), .clk(clk), .rst(rst) );
endmodule

module top_modified(input [3:0] din, din1, output logic [3:0] dout, dout1, input clk, rst);
  top i_top(.*);
  initial 
  begin
    force i_top.i1.din = i_top.din;
  end
endmodule

In this example, the design's top module instantiates two instances of the dff module. din and din1 ports of the top module drive the din port of i0 and i1 instances.

Suppose you want to change the connections in the top module without changing the RTL inside the top module. In this situation, you can use a force statement within a wrapper module (top_modified), which becomes the new top module. In the new top module, use the force statement to modify the connections in the top module such that the din port of both i0 and i1 instances is driven by the same din port of the top module. The force statement uses a cross-module reference (XMR) to access signals in a hierarchy below it. For more information about XMR, refer to Cross-Module Referencing (XMR) in HDL Code.

Note:

For this example, instead of creating a wrapper top_modified that instantiates the top module, you can also create a secondary top-level entity and make the force assignment in it, as shown in the following:

module secondary_top(input [3:0] din, din1, output logic [3:0] dout, dout1, input clk, rst);
initial begin
  force top.i1.din = top.din;
end
endmodule