1.1. Using Provided HDL Templates 1.2. Instantiating IP Cores in HDL 1.3. Inferring Multipliers and DSP Functions 1.4. Inferring Memory Functions from HDL Code 1.5. Register and Latch Coding Guidelines 1.6. General Coding Guidelines 1.7. Designing with Low-Level Primitives 1.8. Cross-Module Referencing (XMR) in HDL Code 1.9. Using force Statements in HDL Code 1.10. Recommended HDL Coding Styles Revision History
126.96.36.199. Use Synchronous Memory Blocks 188.8.131.52. Avoid Unsupported Reset and Control Conditions 184.108.40.206. Check Read-During-Write Behavior 220.127.116.11. Controlling RAM Inference and Implementation 18.104.22.168. Single-Clock Synchronous RAM with Old Data Read-During-Write Behavior 22.214.171.124. Single-Clock Synchronous RAM with New Data Read-During-Write Behavior 126.96.36.199. Simple Dual-Port, Dual-Clock Synchronous RAM 188.8.131.52. True Dual-Port Synchronous RAM 184.108.40.206. Mixed-Width Dual-Port RAM 220.127.116.11. RAM with Byte-Enable Signals 18.104.22.168. Specifying Initial Memory Contents at Power-Up
22.214.171.124. If Performance is Important, Optimize for Speed 126.96.36.199. Use Separate CRC Blocks Instead of Cascaded Stages 188.8.131.52. Use Separate CRC Blocks Instead of Allowing Blocks to Merge 184.108.40.206. Take Advantage of Latency if Available 220.127.116.11. Save Power by Disabling CRC Blocks When Not in Use 18.104.22.168. Initialize the Device with the Synchronous Load (sload) Signal
3.4.1. Apply Complete System-Centric Timing Constraints for the Timing Analyzer 3.4.2. Force the Identification of Synchronization Registers 3.4.3. Set the Synchronizer Data Toggle Rate 3.4.4. Optimize Metastability During Fitting 3.4.5. Increase the Length of Synchronizers to Protect and Optimize 3.4.6. Increase the Number of Stages Used in Synchronizers 3.4.7. Select a Faster Speed Grade Device
22.214.171.124. Modifying Rule Severity Levels
You can increase the severity level of a Design Assistant rule to match the importance of the rule for your design. You cannot decrease the severity level below the default. Design Assistant messages and reports reflect the rule severity level. You can filter and hide rule messages based on the severity level that you specify.
To customize rule severity level, follow these steps:
- Specify initial Design Assistant Settings, as Setting Up Design Assistant describes.
- In the Design Assistant Rule Settings page, select the rule with a Severity that you want to change. You can only change the severity level of parent rules. Subrules for each stage must reflect the parent rule Severity level.
- Click the Severity cell and select Low, Medium, High, Critical, or Fatal. Design Assistant reports the severity level you specify for the rule violations. Fatal violations cause failure of the Compiler stage.
Figure 39. Modifying Rule Severity LevelNote: Fatal violations indicate conditions that cause design failure and therefore cause the Compiler stage to be unsuccessful. You must correct the fatal condition, reduce the rule Severity, or create a rule waiver before proceeding to the next Compiler stage.Figure 40. Messages Report Fatal Rule Violation Causes Compiler Failure
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