Intel® Quartus® Prime Pro Edition User Guide: Design Recommendations

ID 683082
Date 9/26/2022
Document Table of Contents Avoid Unintentional Latch Generation

When you design combinational logic, certain coding styles can create an unintentional latch. For example, when CASE or IF statements do not cover all possible input conditions, synthesis tools can infer latches to hold the output if a new output value is not assigned. Check your synthesis tool messages for references to inferred latches.

If your code unintentionally creates a latch, modify your RTL to remove the latch:

  • Synthesis infers a latch when HDL code assigns a value to a signal outside of a clock edge (for example, with an asynchronous reset), but the code does not assign a value in an edge-triggered design block.
  • Unintentional latches also occur when HDL code assigns a value to a signal in an edge-triggered design block, but synthesis optimizations remove that logic. For example, when a CASE or IF statement tests a condition that only evaluates to FALSE, synthesis removes any logic or signal assignment in that statement during optimization. This optimization may result in the inference of a latch for the signal.
  • Omitting the final ELSE or WHEN OTHERS clause in an IF or CASE statement can also generate a latch. Don’t care (X) assignments on the default conditions are useful in preventing latch generation. For the best logic optimization, assign the default CASE or final ELSE value to don’t care (X) instead of a logic value.

In Verilog HDL designs, use the full_case attribute to treat unspecified cases as don’t care values (X). However, since the full_case attribute is synthesis-only, it can cause simulation mismatches, because simulation tools still treat the unspecified cases as latches.

VHDL Code Preventing Unintentional Latch Creation

Without the final ELSE clause, the following code creates unintentional latches to cover the remaining combinations of the SEL inputs. When you are targeting a Stratix® series device with this code, omitting the final ELSE condition can cause synthesis tools to use up to six LEs, instead of the three it uses with the ELSE statement. Additionally, assigning the final ELSE clause to 1 instead of X can result in slightly more LEs, because synthesis tools cannot perform as much optimization when you specify a constant value as opposed to a don’t care value.

USE IEEE.std_logic_1164.all;

ENTITY nolatch IS
		oput: OUT STD_LOGIC);
END nolatch;

	PROCESS (a,b,c,sel) BEGIN
		IF sel = "00000" THEN
			oput <= a;
		ELSIF sel = "00001" THEN
			oput <= b;
		ELSIF sel = "00010" THEN
			oput <= c;
		ELSE 				  --- Prevents latch inference
			oput <= 'X'; --/
END rtl;

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