Intel® Advisor User Guide

ID 766448
Date 12/16/2022

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Document Table of Contents


Set the cache associativity for modeling CPU cache behavior during Memory Access Patterns analysis.

GUI Equivalent

Project Properties > Analysis Target > Memory Access Patterns Analysis > Advanced > Cache associativity




<integer> is the number of cache locations where one memory entry can be placed: 1 | 2 | 4 | 8 | 16



Actions Modified

collect=map --enable cache-simulation


1 stands for a direct mapped cache, where a memory entry can occupy only one cache line.


Cache simulation modeling applies to the following:

  • Memory Access Patterns analysis - This basic simulation functionality models accurate memory footprints, miss information, and cache line utilization for a downstream Memory Access Patterns report.

  • CPU / Memory Roofline Insights perspective - This enhanced simulation functionality models multiple levels of cache for a downstream Memory-Level Roofline chart or Roofline interactive HTML report.

This option is applicable only to Memory Access Patterns analysis.


Run a Memory Access Patterns analysis. Model four-way associative cache with default cache line and cache set size.

advisor --collect=map --enable-cache-simulation --cachesim-associativity=4 --cachesim-mode=utilization --project-dir=./advi_results -- ./myApplication

See Also