Serial Digital Interface II IP Support Center

You will find information on how to plan, select, design, implement, and verify your Serial Digital Interface II IP cores for Agilex™ 7, Agilex™ 5 and Agilex™ 3, Stratix® 10 SoC, Arria® 10 SoC, Cyclone® 10 GX SoC, Cyclone® 10 LP SoC, Arria® V SoC, Cyclone® V SoC devices. There are also guidelines on how to bring up your system and debug the Serial Digital Interface II IP design.

Get additional support for Agilex™ 7 FPGA Interface Protocol Design, Agilex™ 5 FPGA Interface Protocol Design, and Agilex™ 3 FPGA Interface Protocol Design step-by-step guided journeys for standard development flows surfacing the key critical resources and documentation.

For other devices, search the Device and Product Support Collections.

1. Device and IP Selection

What features are supported in the SDI II FPGA IP?

• You can refer the SDI II FPGA IP User Guide, section 1. SDI II IP Core Quick Reference

Which FPGA Device Family Should I Use?

• You can refer the SDI II FPGA IP User Guide, section 2.3. General Description

What is the SDI II FPGA IP Core FPGA Resource Utilization?

• You can refer the SDI II FPGA IP User Guide, section 2.4. Performance and Resource Utilization

2. Design Flow and IP Integration

Documentation

• IP Core User Guide
• SDI II FPGA IP User Guide

• Agilex™ 7 Devices
• F-Tile SDI II FPGA IP Design Example User Guide

• Agilex™ 5 Devices
  • GTS SDI II FPGA IP Design Example User Guide

• Stratix® 10 Devices
• SDI II Stratix® 10 FPGA IP Design Example User Guide

• Arria® 10 Devices
• SDI II Arria® 10 FPGA IP Design Example User Guide

• Cyclone® 10 GX Devices
• SDI II Cyclone® 10 GX FPGA IP Design Example User Guide

• FPGA IP release notes
• Serial Digital Interface (SDI) II FPGA IP Release Notes

How do I generate the SDI II FPGA IP core?

• Creating a New Quartus® Prime Project

• Launching IP Catalog

• Parameterizing the IP Core
  

How do I generate the SDI II FPGA IP Design Example?

The links below provides step-by-step instruction to generate SDI II FPGA IP Design Example from the Quartus® Prime software:

• Agilex™ 7 Devices
  • Generating the Design

• Agilex™ 5 Devices 
  • Generating the Design

• Stratix® 10 Devices
  • Generating the Design

• Arria® 10 Devices
  • Generating the Design

• Cyclone® 10 GX Devices
  • Generating the Design

How do I compile and test my design?

For Agilex™, Stratix® 10, Arria® 10, and Cyclone® 10 GX devices, the steps to compile and test your SDI II FPGA IP design can be found in the following SDI II FPGA IP Design Example User Guides, under section "Compiling and Testing the Design":

• Agilex™ 7 Devices
  • Compiling and Testing the Design in Hardware
• Agilex™ 5 Devices
  • Compiling and Testing the Design
• Stratix® 10 Devices
  • Compiling and Testing the Design
• Arria® 10 Devices
  • Compiling and Testing the Design
• Cyclone® 10 GX Devices
  • Compiling and Testing the Design

How can I perform SDI II FPGA IP functional simulation?

For Agilex™ F-tile, Stratix®, Arria® 10, and Cyclone® 10 GX devices, below are the steps to generate SDI II FPGA IP functional simulation:

• Enable the simulation option in the SDI II FPGA IP Parameter Editor and generate SDI II FPGA IP Design Example

• Agilex™ 7 Devices
  • Simulating the Design
  • Simulation Testbench

• Agilex™ 5 Devices
  • Simulating the Design
  • Simulation Testbench

• Stratix® 10 Devices
  • Simulating the Design
  • Simulation Testbench

• Arria® 10 Devices
  • Simulating the Design
  • Simulation Testbench

• Cyclone® 10 GX Devices
  • Simulating the Design
  • Simulation Testbench

3. Board Design and Power Management

Pin Connection Guidelines

• Agilex™ 7 Devices
• Agilex™ 7 Device Family Pin Connection Guidelines
• Agilex™ 5 Devices
  • Pin Connection Guidelines: Agilex™ 5 FPGAs and SoCs
• Agilex™ 3 Devices
  • Pin Connection Guidelines: Agilex™ 3 FPGAs and SoCs
• Stratix® 10 Devices
• Stratix® 10 Device Family Pin Connection Guidelines
• Arria® 10 Devices
• Arria® 10 GX, GT, and SX Device Family Pin Connection Guidelines
• Cyclone® 10 GX Devices
• Cyclone® 10 GX Device Family Pin Connection Guidelines

Schematic Review

• Agilex™ 7 Devices
• Agilex™ 7 Device Schematic Review Worksheet

• Agilex™ 5 Devices
  • Agilex™ 5 Device Schematic Review Worksheet
• Agilex™ 3 Devices
  • Agilex™ 3 Device Schematic Review Worksheet

• Stratix® 10 Devices
• Stratix® 10 GX, MX, and SX Schematic Review Worksheet
• Stratix® 10 GX FPGA Development Kit User Guide
• Stratix® 10 SX SoC Development Kit User Guide
• Arria® 10 Devices
• Arria® 10 GX, GT, and SX Schematic Review Worksheet
• Arria® 10 FPGA Development Kit User
• Arria® 10 SoC Development Kit User Guide
• Cyclone® GX 10 Devices
• Cyclone® 10 GX Schematic Review Worksheet
• Cyclone® 10 GX FPGA Development Kit User Guide

Power Management

• Agilex™ 7 Power Management User Guide
• AN 910: Agilex™ 7 Power Distribution Network Design Guidelines
• Agilex™ 5 Power Management User Guide
• Agilex™ 3 Power Management User Guide
• AN 692: Power Sequencing Considerations for Agilex™ 7 Stratix® 10 Arria® 10 and Cyclone® 10 GX Devices
• Early Power Estimator for Stratix® 10 FPGAs User Guide
• Stratix® 10 Power Management User Guide
• Early Power Estimator for Arria® 10 FPGAs User Guide
• AN 711: Power Reduction Features in Arria® 10 Devices
• Early Power Estimator for Cyclone® 10 GX FPGAs User Guide
• Early Power Estimator (EPE) and Power Analyzer
• AN 750: Using the FPGA PDN Tool to Optimize Your Power Delivery Network Design
• Device-Specific Power Deliver Network (PDN) Tool 2.0 User Guide
• AN 721: Creating an FPGA Power Tree
• Quartus® Prime Pro Edition User Guide: Power Analysis and Optimization
• FPGA Power and Thermal Calculator User Guide

Thermal Power Management

• Agilex™ 7 Devices
  • AN 944: Thermal Modeling for Agilex™ 7 FPGAs with the FPGA Power and Thermal Calculator
• Agilex™ 5 Devices
  • Thermal Design User Guide: Agilex™ 5 FPGAs and SoCs
• Agilex™ 3 Devices
  • Thermal Design User Guide: Agilex™ 3 FPGAs and SoCs
• Stratix® 10 Devices
• AN 787: Stratix® 10 Thermal Modeling and Management with the Early Power Estimator
• AN 943: Thermal Modeling for Stratix® 10 FPGAs with the FPGA Power and Thermal Calculator

Power Sequencing

• Agilex™ 7, Stratix® 10, Arria® 10, and Cyclone® 10 GX Devices
• AN 692: Power Sequencing Considerations for Agilex™ 7, Stratix® 10, Arria® 10, and Cyclone® 10 GX Devices

Development Kits

• The following development kits are available for the SDI II IP Core:
• Stratix® 10 GX Signal Integrity Development Kit
• Stratix® 10 TX Signal Integrity Development Kit
• Arria® 10 GX Transceiver Signal Integrity Development Kit
• Cyclone® 10 GX FPGA Development Kit
• Stratix® V GT Transceiver Signal Integrity Development Kit
• Arria® V GX FPGA development kit
• Cyclone® V GT FPGA development kit

4. Design Examples

• Arria® 10 Device
  • Arria® 10 - GX Device Multi-Rate SDI II Pass-Through Using Video & Image Processing Pipeline Reference Design
  • Arria® 10 - Multi Rate (Up to 12G-SDI) SDI II with External VCXO Reference Design
  • Arria® 10 - Triple Rate SDI II VCXO Removal Reference Design
    • AN 746: SDI II Triple-Rate Reference Designs for Arria® 10 Devices
  • Arria® 10 - 12G-SDI Audio Reference Design
• Cyclone® 10 GX Device
  • Cyclone® 10 GX - AN848: Implementing Triple-rate SDI II with Nextera FMC Daughter Card Reference Design

5. Debug

Frequently Asked Questions

For additional information, search the following resources: Documentation, Training Courses, Videos, Design Examples, and Knowledge Base.

Related Links

• FPGAs for Broadcasting and Pro AV Solutions
• SDI II FPGA IP Core
• 3 Gbps SDI Video (SMPTE 424M) White Paper
• SMPTE.org