Serial Digital Interface II IP Support Center

This page is organized into categories that align with a Serial Digital Interface II system design flow from start to finish. You will find information on how to plan, select, design, implement, and verify your Serial Digital Interface II IP cores. There are also guidelines on how to bring up your system and debug the Serial Digital Interface II IP design.

Get support resources for Intel® Agilex, Intel® Stratix® 10, Intel Arria® 10, and Intel Cyclone® 10 devices from the pages below. For other devices, search from the following links: Documentation ArchiveTraining CoursesQuick VideosReference Design, and Knowledge Base.

1. Device and IP Selection

What features are supported in the SDI II Intel® FPGA IP?

Which Intel® FPGA Device Family Should I Use?

What is the SDI II Intel® FPGA IP Core FPGA Resource Utilization?

2. Design Flow and IP Integration

Documentation

IP Core User Guide

Intel Agilex Devices

Intel Stratix 10 Devices

Intel Arria 10 Devices

Intel Cyclone 10 GX Devices

Intel® FPGA IP release notes

How do I generate the SDI II Intel® FPGA IP core?

How do I generate the SDI II Intel® FPGA IP Design Example?

The links below provides step-by-step instruction to generate SDI II Intel® FPGA IP Design Example from the Intel Quartus Prime software:

How do I compile and test my design?

For Intel Agilex, Intel Stratix 10, Intel Arria 10, and Intel Cyclone 10 GX devices, the steps to compile and test your SDI II Intel® FPGA IP design can be found in the following SDI II Intel® FPGA IP Design Example User Guides, under section "Compiling and Testing the Design":

How can I perform SDI II Intel® FPGA IP functional simulation?

For Intel Agilex F-tile, Intel Stratix, Intel Arria 10, and Intel Cyclone 10 GX devices, below are the steps to generate SDI II Intel® FPGA IP functional simulation:

3. Board Design and Power Management

Pin Connection Guidelines

Intel Agilex Devices

Intel Stratix 10 Devices

Intel Arria 10 Devices

Intel Cyclone 10 GX Devices

Schematic Review

Intel Agilex Devices

Intel Stratix 10 Devices

Intel Arria 10 Devices

Intel Cyclone GX 10 Devices

Power Management

Thermal Power Management

Intel Stratix 10 Devices

Power Sequencing

Intel Stratix 10, Intel Cyclone 10 GX, Intel Arria 10, and Intel Agilex Devices

Developement Kits

The following development kits are available for the SDI II IP Core:

5. Debug

Frequently Asked Questions

Ensure to enable option “CRC error output” in the SDI II Intel® FPGA IP Parameter Editor for correct CRC values (not applicable for SD-SDI).

Make sure the clock signal frequency is connected to the correct onboard clock frequency. For example, if the SDI Tx PLL reflck clock signal is configured to 148.5 MHz, then use 148.5 MHz clock chip as well to connect to SDI Tx PLL refclk signal.

For serial loopback example design, customer can see all the supported video resolution in .tcl file at this directory <example design folder>\hwtest\tpg_ctrl.tcl. For parallel loopback example design, this .tcl file is not available, but customer can still access all the supported video resolution in SMPTE specification.

Make sure the clock signal frequency is connected to the correct onboard clock frequency. For example, if the SDI Tx PLL reflck clock signal is configured to 148.5 MHz, then use 148.5 MHz clock chip as well to connect to SDI Tx PLL refclk signal.

For serial loopback example design, customer can see all the supported video resolution in .tcl file at this directory <example design folder>\hwtest\tpg_ctrl.tcl. For parallel loopback example design, this .tcl file is not available, but customer can still access all the supported video resolution in SMPTE specification.