SDI II Intel® FPGA IP Core

The serial digital interface (SDI) II Intel FPGA intellectual property (IP) core implements a transmitter, receiver or full-duplex SDI at standard definition, high definition or 3G to 12G rate as defined by the Society of Motion Picture and Television Engineers. The SDI II IP core supports multiple standards. These modes provide automatic receiver rate detection and transceiver dynamic reconfiguration.

Read the SDI II Intel FPGA IP user guide ›

Read the SDI Audio Intel FPGA IP user guide ›

Read the SDI II Intel® Arria® 10 FPGA IP design example user guide ›

Read the SDI II Intel® Stratix® 10 FPGA IP design example user guide ›

Read the SDI II Intel® Cyclone® 10 GX FPGA IP design example user guide ›

SDI II Intel® FPGA IP Core

Features

IP Core Feature

Description

Transceiver data interface

20 bit, 40 bit, and 80 bit

Supported SDI standards and video formats
  • Single Standard
  • Standard Definition or SD-SDI
  • High Definition or HD-SDI
  • 3 gigabits per second (Gbps) or 3G-SDI
  • Dual Link HD-SDI
  • Multiple Standards
  • Dual Standard up to HD-SDI
  • Triple Standard up to 3G-SDI
  • Multi Standard up to 12G-SDI

Note: Not all devices support all formats, see “Device Support” below

SMPTE support

  • SMPTE425M level A support (direct source image formatting)
  • SMPTE425M level B support (dual link mapping)
Other features
  • Payload identification packet insertion and extraction
  • Clock enable generator
  • Video rate detection
  • Cyclic redundancy check (CRC) encoding and decoding (except SD)
  • Dual link data stream synchronization (only HD)

Device Support

 

Single Standard

Multiple Standards

Device Family

SD-SDI

HD-SDI

3G-SDI

Dual Link

HD-SDI

Dual Standard

(up to HD)

Triple Standard

(up to 3G)

Multi Standard

(up to 12G)

Intel® Stratix® 10

-

 

-

Intel® Cyclone® 10

-

 

-

Intel® Arria® 10

-

 

-

Stratix® V

-

Cyclone® V

-

Arria® V GX

-

Arria® V GZ

-

IP Quality Metrics

Basics

Year IP was first released

2006

Latest version of Intel® Quartus® Prime software supported?

Yes

Status

Production

Deliverables

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim*- Intel® FPGA Edition
  • Timing and/or layout constraints
  • Testbench or design example
  • Documentation with revision control
  • Readme file
  • Yes
  • Yes
  • Yes
  • Yes
  • Yes
  • No

Any additional customer deliverables provided with IP

None

Parameterization GUI allowing end user to configure IP

Yes

IP core is enabled for the Intel FPGA IP Evaluation Mode Support

Yes

Source language

Both Verilog and VHDL

Testbench language

Both Verilog and VHDL

Software drivers provided

No

Driver operating system (OS) support

N/A

Implementation

User interface

Other (Parallel Video)

IP-XACT metadata

No

Verification

Simulators supported

ModelSim*, VCS, Riviera-PRO, Xcelium

Hardware validated

Intel® Stratix® 10, Intel® Cyclone® 10, Intel® Arria® 10, Stratix® V, Cyclone V, Arria V GX/GZ

Industry standard compliance testing performed

No

If Yes, which test(s)?

N/A

If Yes, on which Intel FPGA device(s)?

N/A

If Yes, date performed

N/A

If No, is it planned?

No

Interoperability

IP has undergone interoperability testing

Yes

If yes, on which Intel FPGA device(s)

Intel® Stratix® 10, Intel Cyclone 10, Intel Arria 10, Stratix V, Cyclone V, Arria V

Interoperability reports available

Contact Sales

Getting Started

Video Tutorials

The following video tutorials are available for you to learn about using this IP.