The serial digital interface (SDI) II Intel FPGA intellectual property (IP) core implements a transmitter, receiver or full-duplex SDI at standard definition, high definition or 3G to 12G rate as defined by the Society of Motion Picture and Television Engineers. The SDI II IP core supports multiple standards. These modes provide automatic receiver rate detection and transceiver dynamic reconfiguration.
This video demonstrates how to implement an SDI II IP core in an Intel Arria 10 device. You will be guided through step by step generation in Intel® Quartus® Prime software for all necessary transceiver-related components and integration.
Intel® Agilex™ 7 FPGA F-Tile enables SDI IP supporting SD-SDI up to 12G-SDI. This demonstration runs the SDI Multi-Rate Retransmit Design without an external VCXO on the Intel® Agilex™ 7 FPGA I-Series Transceiver-SoC Development Kit.