GTS Ethernet Hard IP User Guide: Agilex™ 3 FPGAs and SoCs
ID
848477
Date
7/07/2025
Public
1. Overview
2. Install and License the GTS Ethernet Hard IP
3. Configure and Generate Ethernet Hard IP variant
4. Integrate GTS Ethernet Hard IP into Your Application
5. Simulate and Compile (MAC+PCS) Design Example
6. Simulate and Compile (MII PCS Only/PCS66 OTN/PCS66 FlexE) Design Example
7. Simulate and Compile SyncE Design Example
8. Simulate and Compile PTP1588 Design Example
9. Simulate and Compile (Dynamically Reconfigurable Ethernet Mode)
10. Simulate and Compile - Auto-Negotiation and Link Training
11. Troubleshoot and Diagnose Issues
12. Appendix A: Functional Description
13. Appendix B: Configuration Registers
14. Appendix C: Document Revision History for the GTS Ethernet Hard IP User Guide: Agilex 3 FPGAs and SoCs
4.1. Implement Required Clocking
4.2. Implement Required Resets
4.3. Connect the Status Interface
4.4. Connect the MAC Avalon Streaming Client Interface
4.5. Connect the MII PCS Only Client Interface
4.6. Connect the PCS66 Client Interface – FlexE and OTN
4.7. Connect the Precision Time Protocol Interface
4.8. Connect the Ethernet Hard IP Reconfiguration Interface
4.9. Connect the Auto-Negotiation and Link Training
4.10. Connect the Multirate Auto-Negotiation and Link Training
4.11. Connect the Dynamically Reconfigurable Ethernet Mode
4.4.1.1. Drive the Ethernet Packet to the TX MAC Avalon Streaming Client Interface with Disabled Preamble Passthrough
4.4.1.2. Drive the Ethernet Packet on the TX MAC Avalon Streaming Client Interface with Enabled Preamble Passthrough
4.4.1.3. Use i_tx_skip_crc to Control Source Address, PAD, and CRC Insertion
4.4.1.4. Assert the i_tx_error to Invalidate a Packet
4.4.2.1. Receive Ethernet Frame on the RX MAC Avalon Streaming Client Interface with Preamble Passthrough Disabled
4.4.2.2. Receive Ethernet Frame with Preamble Passthrough Enabled
4.4.2.3. Receive Ethernet Frame with Remove CRC bytes Disabled
4.4.2.4. Monitor Status and Errors on the RX MAC Avalon Streaming Client Interface
8.3. Simulate the Design Example
The simulation testbench sends and receives 16 packets per each instantiated IP using the ROM-based packet generator.
Figure 61. Design Example Simulation Block Diagram
The following steps describe how to simulate the design example:
- At the command prompt, change the directory to <design_example_dir>/example_testbench.
- Run the simulation script for the supported simulator of your choice. The script compiles and runs the testbench in the simulator. Refer to the following table Steps to Simulate the Testbench.
Simulator Instructions Synopsys* VCS* MX In the command line, type the following command: sh run_vcsmx.sh
QuestaSim* or Questa* Intel® FPGA Edition To run a simulation in GUI, type the following command: vsim -do run_vsim.do
If you prefer to simulate without bringing up the GUI, type the following command:vsim -c -do run_vsim.do
Xcelium* In the command line, type the following command: sh run_xcelium.sh
Aldec Riviera-PRO* 9 In the command line, type: vsim -c -do run_rivierasim.do
To enable Synopsys* VCS* Verdi, uncomment the following line from the testbench file located in <design_example_dir>/example_testbench/basic_avl_tb_top.sv.//$fsdbDumpvars(0, "+all", basic_avl_tb_top); //$wlfdumpvars(0);
A successful simulation ends with the following message:Testbench complete
After successful completion, analyze the results.
9 Supports Riviera 2024.04