GTS Ethernet Hard IP User Guide: Agilex™ 3 FPGAs and SoCs

ID 848477
Date 7/07/2025
Public
Document Table of Contents

12.4.4. Reference Time Interval

Table below displays the number of bits between two subsequent reference time captures. The UI adjustment calculation uses these numbers. To speed up the simulation, the number for simulation is smaller.

Table 65.  Reference Time (TAM) Interval
FEC type:
  • No FEC: No FEC
  • CL74: IEEE 802.3 BASE-R Firecode (CL74)
Speed FEC Type Simulation (bit)
TX

RX 14

10GE No FEC 168,960 168,960
14 Depends on the link partner AM. The numbers assume serial loopback.