GTS Ethernet Hard IP User Guide: Agilex™ 3 FPGAs and SoCs
ID
848477
Date
7/07/2025
Public
1. Overview
2. Install and License the GTS Ethernet Hard IP
3. Configure and Generate Ethernet Hard IP variant
4. Integrate GTS Ethernet Hard IP into Your Application
5. Simulate and Compile (MAC+PCS) Design Example
6. Simulate and Compile (MII PCS Only/PCS66 OTN/PCS66 FlexE) Design Example
7. Simulate and Compile SyncE Design Example
8. Simulate and Compile PTP1588 Design Example
9. Simulate and Compile (Dynamically Reconfigurable Ethernet Mode)
10. Simulate and Compile - Auto-Negotiation and Link Training
11. Troubleshoot and Diagnose Issues
12. Appendix A: Functional Description
13. Appendix B: Configuration Registers
14. Appendix C: Document Revision History for the GTS Ethernet Hard IP User Guide: Agilex 3 FPGAs and SoCs
4.1. Implement Required Clocking
4.2. Implement Required Resets
4.3. Connect the Status Interface
4.4. Connect the MAC Avalon Streaming Client Interface
4.5. Connect the MII PCS Only Client Interface
4.6. Connect the PCS66 Client Interface – FlexE and OTN
4.7. Connect the Precision Time Protocol Interface
4.8. Connect the Ethernet Hard IP Reconfiguration Interface
4.9. Connect the Auto-Negotiation and Link Training
4.10. Connect the Multirate Auto-Negotiation and Link Training
4.11. Connect the Dynamically Reconfigurable Ethernet Mode
4.4.1.1. Drive the Ethernet Packet to the TX MAC Avalon Streaming Client Interface with Disabled Preamble Passthrough
4.4.1.2. Drive the Ethernet Packet on the TX MAC Avalon Streaming Client Interface with Enabled Preamble Passthrough
4.4.1.3. Use i_tx_skip_crc to Control Source Address, PAD, and CRC Insertion
4.4.1.4. Assert the i_tx_error to Invalidate a Packet
4.4.2.1. Receive Ethernet Frame on the RX MAC Avalon Streaming Client Interface with Preamble Passthrough Disabled
4.4.2.2. Receive Ethernet Frame with Preamble Passthrough Enabled
4.4.2.3. Receive Ethernet Frame with Remove CRC bytes Disabled
4.4.2.4. Monitor Status and Errors on the RX MAC Avalon Streaming Client Interface
12.4.2.1. PTP TX User Flow
The following flows depict pseudo-code meant for the conceptual, illustrative purposes. For definitive software routines, refer to the design example.
Important: If IP undergoes TX reset at any point in this flow, you must restart the entire PTP TX client flow.
- After power up or a TX reset, wait until TX raw offset data are ready.
Monitor the status via one of the following:
- Output port:
o_tx_ptp_offset_data_valid = 1'b1
- Polling via Avalon® memory-mapped interface register until it is asserted:
csr_read(ptp_status.tx_ptp_offset_data_valid) = 1’b1
- Output port:
- Read TX raw offset data from IP:
tx_const_delay = csr_read(ptp_tx_lane_calc_data_constdelay[30:0]) tx_const_delay_sign = csr_read(ptp_tx_lane_calc_constdelay[31]) tx_apulse_offset = csr_read(ptp_tx_lane_calc_data_offset[30:0]) tx_apulse_offset_sign = csr_read(ptp_tx_lane_calc_data_offset[31]) tx_apulse_wdelay = csr_read(ptp_tx_lane_calc_data_wiredelay[19:0]) }
- Calculate TX offsets:
- Calculate TX TAM adjust:
tx_tam_adjust = (tx_const_delay_sign ? –tx_const_delay : tx_const_delay) + (tx_apulse_offset_sign? –tx_apulse_offset : tx_apulse_offset) – (tx_apulse_wdelay)
Note: Convert TAM adjust to a 32-bit 2's complement number:tx_tam_adjust_2c = tx_tam_adjust
- Calculate TX extra latency:
Convert unit of TX PMA delay from UI to nanoseconds. For UI value, refer to tables specified in UI Value and PMA Delay.
tx_pma_delay_ns = tx_pma_delay_ui * UI12
TX extra latency is a positive adjustment. To indicate the positive adjustment, set the most-significant register bit to 0. Total up all extra latency together:tx_extra_latency[31] = 1'b0 tx_extra_latency[30:0] = tx_pma_delay_ns + tx_external_phy_delay
- Calculate TX TAM adjust:
- Write the calculated TX offsets to IP:
- Write TX extra latency:
csr_write(tx_ptp_extra_latency, tx_extra_latency)
- Write TX TAM adjust:
csr_write(ptp_tx_tam_adjust, tx_tam_adjust_2c)
- Write TX extra latency:
- UI value measurement. Follow the steps mentioned in the Adjust TX UI section.
For simulation or hardware run with 0 PPM setup, you can skip the measurement and program 0 PPM UI value defined in UI Adjustment.
- Notify soft PTP that the user flow configuration is complete.
csr_write(ptp_tx_user_cfg_status.tx_user_cfg_done, 1'b1)
- Wait until TX PTP is ready.
You can monitor the status via one of the following:
- Output port:
o_tx_ptp_ready = 1'b1
- Polling via CSR:
csr_read(ptp_status.tx_ptp_ready) = 1’b1
- Output port:
- TX PTP is up and running.
Adjust TX UI value.
Perform the TX UI adjustment occasionally to prevent time counter drift from golden time-of-day in the system. Follow the steps described in Adjust TX UI.
Note: UI measurement is a long process in simulation. Therefore, for simulation, Intel recommends skipping this step and program a 0 PPM value.
12 The UI format differs from the format of other variables. UI uses the {4-bit ns, 28-bit fractional ns} format. Other variables defined in this flow use the {N-bit ns, 16-bit fractional ns} format, where N is the largest number to store the calculation's maximum value. If you use UI format in your calculation, you must convert your result to a 16-bit fractional ns format.