GTS Ethernet Hard IP User Guide: Agilex™ 3 FPGAs and SoCs

ID 848477
Date 7/07/2025
Public
Document Table of Contents

4.1.4. Implement Clock Connections in PTP-Based Design

When you enable Enable IEEE 1588 PTP parameter in your IP, you must clock all Ethernet IP cores with the same system clock source o_clk_pll of the PTP adapter. The required input clock source is a system clock source divided by 2, with a minimum frequency of 402.83 MHz.

When you enable Enable asynchronous adapter clocks along with the Enable IEEE 1588 PTP parameter in your IP, the i_clk_pll signal must connect to the same system clock source. The i_clk_tx and i_clk_rx input clock signals can be asynchronous with respect to each other and o_clk_pll, as long as they are fast enough to ensure the IP core channel processes all data successfully.

The PTP adapter's i_clk_sys clock is sourced from its own o_clk_pll clock.

Figure 21. Clock Connections in PTP-Based Synchronous Operation
Figure 22. Clock Connections in PTP-Based Asynchronous Operation