GTS Ethernet Hard IP User Guide: Agilex™ 3 FPGAs and SoCs

ID 848477
Date 7/07/2025
Public
Document Table of Contents

1.2. High-Level Functional Overview

The GTS Ethernet Hard IP along with other supporting IPs allows you to create various Ethernet solutions. The following figure shows the conceptual view of TX/RX Datapath.

Figure 1. GTS Ethernet Hard IP Conceptual TX/RX Datapath

The TX/RX Avalon® streaming interface (Avalon® ST) is used to access the GTS Ethernet Hard IP from the FPGA fabric. The TX and RX datapath begins at the core interface and progresses through MAC, PCS, FEC (optional), and PMA. The Ethernet implementation integrates all of these components; however for OTN and FlexE applications, a direct PCS mode is used, which supports a direct connection to the PCS block via the PCS66 interface.