GTS Ethernet Hard IP User Guide: Agilex™ 3 FPGAs and SoCs

ID 848477
Date 7/07/2025
Public
Document Table of Contents

1.6. GTS Ethernet Hard IP Design Flow

The following flowchart illustrates the GTS Ethernet Hard IP design flow for Ethernet general mode designs:

Figure 2. Design Flow

For Dynamically Reconfigurable Ethernet mode designs, refer to the GTS Dynamic Reconfiguration Controller IP Design Flow.

The GTS Ethernet Hard IP provides a simulation testbench and a hardware design example. When you generate the design example, the parameter editor automatically creates an example design with all necessary files for simulation and compilation based on the provided qsf settings as per the OPN for Agilex® 3 devices. For more details, refer to Generate GTS EHIP Design Example.