GTS Ethernet Hard IP User Guide: Agilex™ 3 FPGAs and SoCs

ID 848477
Date 7/07/2025
Public
Document Table of Contents

12.4.1. Features

GTS Ethernet Hard IP supports the following PTP features:
  • Latency registers to accommodate for delay of external PHY components
  • 10GE

    operating speed
  • 1-step update 1588v2 96-bit timestamp
  • 1-step update residence time in correction field
  • 1-step set UPD/IPv4 checksum to zero
  • 1-step update is performed to update 2 bytes of the extended byte to ensure the UDP checksum remains correct
  • 1-step asymmetry delay adjustment in correction field
  • 1-step peer-to-peer mean path delay adjustment in correction field
  • PTP statistics to keep track of number of packets with a PTP timestamp operation in TX and RX path
  • Avalon® memory-mapped interface accessible configuration, debug, and status registers
  • Timestamp accuracy in Advanced Mode: 10G: +/- 1.5ns, when 1PPS is enabled, the accuracy is: +/- 2.5 ns
    Note: GTS Ethernet Hard IP does not support basic mode.