GTS Ethernet Hard IP User Guide: Agilex™ 3 FPGAs and SoCs
ID
848477
Date
7/07/2025
Public
1. Overview
2. Install and License the GTS Ethernet Hard IP
3. Configure and Generate Ethernet Hard IP variant
4. Integrate GTS Ethernet Hard IP into Your Application
5. Simulate and Compile (MAC+PCS) Design Example
6. Simulate and Compile (MII PCS Only/PCS66 OTN/PCS66 FlexE) Design Example
7. Simulate and Compile SyncE Design Example
8. Simulate and Compile PTP1588 Design Example
9. Simulate and Compile (Dynamically Reconfigurable Ethernet Mode)
10. Simulate and Compile - Auto-Negotiation and Link Training
11. Troubleshoot and Diagnose Issues
12. Appendix A: Functional Description
13. Appendix B: Configuration Registers
14. Appendix C: Document Revision History for the GTS Ethernet Hard IP User Guide: Agilex 3 FPGAs and SoCs
4.1. Implement Required Clocking
4.2. Implement Required Resets
4.3. Connect the Status Interface
4.4. Connect the MAC Avalon Streaming Client Interface
4.5. Connect the MII PCS Only Client Interface
4.6. Connect the PCS66 Client Interface – FlexE and OTN
4.7. Connect the Precision Time Protocol Interface
4.8. Connect the Ethernet Hard IP Reconfiguration Interface
4.9. Connect the Auto-Negotiation and Link Training
4.10. Connect the Multirate Auto-Negotiation and Link Training
4.11. Connect the Dynamically Reconfigurable Ethernet Mode
4.4.1.1. Drive the Ethernet Packet to the TX MAC Avalon Streaming Client Interface with Disabled Preamble Passthrough
4.4.1.2. Drive the Ethernet Packet on the TX MAC Avalon Streaming Client Interface with Enabled Preamble Passthrough
4.4.1.3. Use i_tx_skip_crc to Control Source Address, PAD, and CRC Insertion
4.4.1.4. Assert the i_tx_error to Invalidate a Packet
4.4.2.1. Receive Ethernet Frame on the RX MAC Avalon Streaming Client Interface with Preamble Passthrough Disabled
4.4.2.2. Receive Ethernet Frame with Preamble Passthrough Enabled
4.4.2.3. Receive Ethernet Frame with Remove CRC bytes Disabled
4.4.2.4. Monitor Status and Errors on the RX MAC Avalon Streaming Client Interface
11.1.3. Enable PCS Loopback
The output of the TX PCS is connected to the input of the RX PCS, forming a loopback connection.
Figure 69. Enable PCS Loopback
Follow these steps to enable PCS Loopback Mode:
- Write 0x1 to bit 0 of the eio_sys_rst(0x108) to reset the GTS Ethernet Intel® FPGA IP.
- If internal serial loopback is enabled, disable it by:
- Writing 0x0A340 to address 0xA403C
- Poll address 0xA4040 until bit 14 = 0 and bit 15 = 1
- Write 0x02340 to address 0xA403C
- Poll address 0xA4040 until bit 14 = 0 and bit 15 = 0
- Perform PCS loopback write bit [18:16] of 32 bit register 0x60048 with 0x3.
- Write 0x1 to bit 0 of ignore_rx_lock2data (0x10018).
- Deassert the soft global reset by writing 0x0 to bit 0 of eio_sys_rst (0x108).
- Write 0x1 to bit 0 of hardware packet client control hw_pc_ctrl register at address 0x00 to instruct the packet client to transmit data and start the packet generator. Alternatively, write 0x1 to 0x100000 register.
- Check MAC statistics by running the command chkmac_stats.