GTS Ethernet Hard IP User Guide: Agilex™ 3 FPGAs and SoCs

ID 848477
Date 7/07/2025
Public
Document Table of Contents

8.1. Design Example Features

The design example provides the following basic functionality:
  • Send, receive, and check 16 data packets using the packet generator.
  • Perform Avalon® Memory-Mapped Interface test.