GTS Ethernet Hard IP User Guide: Agilex™ 3 FPGAs and SoCs
ID
848477
Date
7/07/2025
Public
1. Overview
2. Install and License the GTS Ethernet Hard IP
3. Configure and Generate Ethernet Hard IP variant
4. Integrate GTS Ethernet Hard IP into Your Application
5. Simulate and Compile (MAC+PCS) Design Example
6. Simulate and Compile (MII PCS Only/PCS66 OTN/PCS66 FlexE) Design Example
7. Simulate and Compile SyncE Design Example
8. Simulate and Compile PTP1588 Design Example
9. Simulate and Compile (Dynamically Reconfigurable Ethernet Mode)
10. Simulate and Compile - Auto-Negotiation and Link Training
11. Troubleshoot and Diagnose Issues
12. Appendix A: Functional Description
13. Appendix B: Configuration Registers
14. Appendix C: Document Revision History for the GTS Ethernet Hard IP User Guide: Agilex 3 FPGAs and SoCs
4.1. Implement Required Clocking
4.2. Implement Required Resets
4.3. Connect the Status Interface
4.4. Connect the MAC Avalon Streaming Client Interface
4.5. Connect the MII PCS Only Client Interface
4.6. Connect the PCS66 Client Interface – FlexE and OTN
4.7. Connect the Precision Time Protocol Interface
4.8. Connect the Ethernet Hard IP Reconfiguration Interface
4.9. Connect the Auto-Negotiation and Link Training
4.10. Connect the Multirate Auto-Negotiation and Link Training
4.11. Connect the Dynamically Reconfigurable Ethernet Mode
4.4.1.1. Drive the Ethernet Packet to the TX MAC Avalon Streaming Client Interface with Disabled Preamble Passthrough
4.4.1.2. Drive the Ethernet Packet on the TX MAC Avalon Streaming Client Interface with Enabled Preamble Passthrough
4.4.1.3. Use i_tx_skip_crc to Control Source Address, PAD, and CRC Insertion
4.4.1.4. Assert the i_tx_error to Invalidate a Packet
4.4.2.1. Receive Ethernet Frame on the RX MAC Avalon Streaming Client Interface with Preamble Passthrough Disabled
4.4.2.2. Receive Ethernet Frame with Preamble Passthrough Enabled
4.4.2.3. Receive Ethernet Frame with Remove CRC bytes Disabled
4.4.2.4. Monitor Status and Errors on the RX MAC Avalon Streaming Client Interface
8.2. Design Example Components
Figure 60. IP Core Instantiation with IEEE 1588v2 Precision Time Protocol (PTP) Design Example Block Diagram
The GTS Ethernet Hard IP with IEEE 1588v2 design example includes the following components:
Design Component | Description |
---|---|
GTS Ethernet Hard IP | Instantiates the GTS Ethernet Hard IP (intel_eth_gts) with any supported configuration as shown in Simulate and Compile (MAC+PCS) Design Example. |
GTS System PLL Clocks GTS Ethernet Hard IP | Provides the system clock i_clk_sys signal to the GTS Ethernet Hard IP . |
GTS Reset Sequencer GTS Ethernet Hard IP | Provides the PMA Control Unit clock i_pma_cu_clk to the GTS Ethernet Hard IP . |
Packet Client | Generates traffic pattern for MAC mode and non-MAC modes. The Packet Client does not support the PTP functionality when packet loop back is set from RX to TX in client side. |
Avalon® Memory-Mapped Interface Decoder | Decodes the Avalon® memory-mapped interface address. |
Time-of-Delay | Provides a continuous flow of a current time-of-day information to the IP. The master TOD runs at 125 MHz clock frequency. TX TOD and RX TOD, which are clocked by div66 or div68 clock of the GTS Ethernet Hard IP, synchronize to the master TOD through their respective TOD synchronizers. In this user guide, the generated design example assumes a 0 ppm delay. In your design, drive the master TOD with the most accurate clock. |
PTP Command Generator | The PTP command generation module in the Packet Client generates a PTP command for the packet in transmission. The generated command aligns with the start-of-packet (SOP) for the Avalon® streaming interface. |
Packet Monitor | Stores sent and received packet information between the packet client and the IP core. |
PTP Monitor | Stores the PTP information sent from the Packet Client to the GTS Ethernet Hard IP and vice versa when the packet loops back from the TX serial to the RX serial. |