GTS Ethernet Hard IP User Guide: Agilex™ 3 FPGAs and SoCs

ID 848477
Date 7/07/2025
Public
Document Table of Contents

8.2. Design Example Components

Figure 60.  IP Core Instantiation with IEEE 1588v2 Precision Time Protocol (PTP) Design Example Block Diagram
The GTS Ethernet Hard IP with IEEE 1588v2 design example includes the following components:
Design Component Description
GTS Ethernet Hard IP Instantiates the GTS Ethernet Hard IP (intel_eth_gts) with any supported configuration as shown in Simulate and Compile (MAC+PCS) Design Example.
GTS System PLL Clocks GTS Ethernet Hard IP Provides the system clock i_clk_sys signal to the GTS Ethernet Hard IP .
GTS Reset Sequencer GTS Ethernet Hard IP Provides the PMA Control Unit clock i_pma_cu_clk to the GTS Ethernet Hard IP .
Packet Client Generates traffic pattern for MAC mode and non-MAC modes. The Packet Client does not support the PTP functionality when packet loop back is set from RX to TX in client side.
Avalon® Memory-Mapped Interface Decoder Decodes the Avalon® memory-mapped interface address.
Time-of-Delay Provides a continuous flow of a current time-of-day information to the IP. The master TOD runs at 125 MHz clock frequency. TX TOD and RX TOD, which are clocked by div66 or div68 clock of the GTS Ethernet Hard IP, synchronize to the master TOD through their respective TOD synchronizers. In this user guide, the generated design example assumes a 0 ppm delay. In your design, drive the master TOD with the most accurate clock.
PTP Command Generator The PTP command generation module in the Packet Client generates a PTP command for the packet in transmission. The generated command aligns with the start-of-packet (SOP) for the Avalon® streaming interface.
Packet Monitor Stores sent and received packet information between the packet client and the IP core.
PTP Monitor Stores the PTP information sent from the Packet Client to the GTS Ethernet Hard IP and vice versa when the packet loops back from the TX serial to the RX serial.