GTS Ethernet Hard IP User Guide: Agilex™ 3 FPGAs and SoCs

ID 848477
Date 7/07/2025
Public
Document Table of Contents

6.2. Design Example Components

When generating a design example, the software instantiates specific components as mentioned in the table below.

Figure 56.  10GE Design Example Block Diagram
The GTS Ethernet Hard IP design example includes the following components:
Design Component Description
GTS Ethernet Hard IP Instantiates the GTS Ethernet Hard IP (intel_eth_gts) with any supported configuration as shown in Simulate and Compile (MAC+PCS) Design Example.
GTS System PLL Clocks IP Provides the system clock i_clk_sys signal to the GTS Ethernet Hard IP .
GTS Reset Sequencer IP Provides the PMA Control Unit clock i_pma_cu_clk to the GTS Ethernet Hard IP .
Packet Client Generates traffic pattern for MAC mode and non-MAC modes.
Avalon® Memory-Mapped Interface Decoder Decodes the Avalon® memory-mapped interface address.