GTS Ethernet Hard IP User Guide: Agilex™ 3 FPGAs and SoCs
ID
848477
Date
7/07/2025
Public
1. Overview
2. Install and License the GTS Ethernet Hard IP
3. Configure and Generate Ethernet Hard IP variant
4. Integrate GTS Ethernet Hard IP into Your Application
5. Simulate and Compile (MAC+PCS) Design Example
6. Simulate and Compile (MII PCS Only/PCS66 OTN/PCS66 FlexE) Design Example
7. Simulate and Compile SyncE Design Example
8. Simulate and Compile PTP1588 Design Example
9. Simulate and Compile (Dynamically Reconfigurable Ethernet Mode)
10. Simulate and Compile - Auto-Negotiation and Link Training
11. Troubleshoot and Diagnose Issues
12. Appendix A: Functional Description
13. Appendix B: Configuration Registers
14. Appendix C: Document Revision History for the GTS Ethernet Hard IP User Guide: Agilex 3 FPGAs and SoCs
4.1. Implement Required Clocking
4.2. Implement Required Resets
4.3. Connect the Status Interface
4.4. Connect the MAC Avalon Streaming Client Interface
4.5. Connect the MII PCS Only Client Interface
4.6. Connect the PCS66 Client Interface – FlexE and OTN
4.7. Connect the Precision Time Protocol Interface
4.8. Connect the Ethernet Hard IP Reconfiguration Interface
4.9. Connect the Auto-Negotiation and Link Training
4.10. Connect the Multirate Auto-Negotiation and Link Training
4.11. Connect the Dynamically Reconfigurable Ethernet Mode
4.4.1.1. Drive the Ethernet Packet to the TX MAC Avalon Streaming Client Interface with Disabled Preamble Passthrough
4.4.1.2. Drive the Ethernet Packet on the TX MAC Avalon Streaming Client Interface with Enabled Preamble Passthrough
4.4.1.3. Use i_tx_skip_crc to Control Source Address, PAD, and CRC Insertion
4.4.1.4. Assert the i_tx_error to Invalidate a Packet
4.4.2.1. Receive Ethernet Frame on the RX MAC Avalon Streaming Client Interface with Preamble Passthrough Disabled
4.4.2.2. Receive Ethernet Frame with Preamble Passthrough Enabled
4.4.2.3. Receive Ethernet Frame with Remove CRC bytes Disabled
4.4.2.4. Monitor Status and Errors on the RX MAC Avalon Streaming Client Interface
4.11. Connect the Dynamically Reconfigurable Ethernet Mode
To create a GTS Ethernet Hard IP in Reconfiguration mode with Dynamic Reconfiguration Controller IP enabled, the following four components are required:
- GTS Ethernet Hard IP
- GTS Dynamic Reconfiguration Controller IP
- System PLL IP, which generates a system clock for the Ethernet IP
- Reset Sequencer IP
Refer to the GTS Dynamic Reconfiguration Controller IP User Guide for instructions on generating and configuring a dynamic reconfiguration design.
The following diagram illustrates the interconnection signals required for the GTS Ethernet Hard IP with Dynamic Reconfiguration Controller IP. After generating the four required components, connect them as depicted in the following diagram:
Figure 52. IP
The following diagram specifies the signals positioned between the GTS EHIP Hard IP and the DR Controller IP:
Figure 53. Interface signals between the GTS EHIP Hard IP and the DR Controller IP
Multirate Top Name | Direction of MR Top Name | Dynamic Reconfiguration Controller IP name | Description |
---|---|---|---|
i_dr_lavmm_addr_ch0 | Input | dr_ch0_lavmm_addr | Address from DR controller to DR MUX within Multirate RIP |
i_dr_lavmm_be_ch0 | Input | dr_ch0_lavmm_be | Byte enable for HIP from DR controller |
i_dr_lavmm_clk_ch0 | Input | i_reconfig_clk | Clocks for CSRs to DR MUX |
i_dr_lavmm_read_ch0 | Input | dr_ch0_lavmm_read | Read enable for HIP from DR controller |
i_dr_lavmm_rstn_ch0 | Input | dr_ch0_lavmm_rstn | The clock gating signal towards HIP (not reset) is used to avoid glitches during startup. |
i_dr_lavmm_wdata_ch0 | Input | dr_ch0_lavmm_wdata | Write data from HIP |
i_dr_lavmm_write_ch0 | Input | dr_ch0_lavmm_write | Write enable for HIP from DR controller |
i_src_pause_request_ch0 | Input | dr_src_pause_request | Request pause to Channel SRC from DR controller |
o_dr_lavmm_rdata_ch0 | Output | dr_ch0_lavmm_rdata | Read data from HIP to DR controller |
o_dr_lavmm_rdata_valid | Output | dr_ch0_lavmm_rdata_valid | Read data valid from HIP to DR controller |
o_dr_lavmm_waitreq_ch0 | Output | dr_ch0_lavmm_waitreq | Wait request from Hard IP to DR controller |
o_src_pause_grant_ch0 | Output | dr_src_pause_grant | Pause granted by SRC to DR controller |
one_hot_sel | Input | dr_one_hot_sel | The one-hot selector indicates the current active profiles. It is used to select the currently active protocol IPs. |
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