Agilex™ 3 FPGAs and SoCs Device Data Sheet

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ID 848370
Date 8/11/2025
Public
Document Table of Contents
Document Table of Contents x
Agilex™ 3 FPGAs and SoCs Device Data Sheet
Agilex™ 3 FPGAs and SoCs Device Data Sheet x
Electrical Characteristics Switching Characteristics Configuration Specifications I/O Timing Programmable IOE Delay Glossary Document Revision History for the Agilex 3 FPGAs and SoCs Device Data Sheet
Electrical Characteristics x
Operating Conditions
Operating Conditions x
Absolute Maximum Ratings Maximum Allowed Overshoot and Undershoot Voltage Recommended Operating Conditions DC Characteristics I/O Standard Specifications
Recommended Operating Conditions x
Recommended Operating Conditions GTS Transceiver Power Supply Operating Conditions HPS Power Supply Operating Conditions
DC Characteristics x
Supply Current and Power Consumption HSIO DC Characteristics HVIO DC Characteristics HPS I/O DC Characteristics SDM I/O DC Characteristics
HSIO DC Characteristics x
HSIO I/O Pin Leakage Current HSIO OCT Calibration Accuracy Specifications HSIO OCT Without Calibration Resistance Tolerance Specifications HSIO Pin Capacitance HSIO Internal Weak Pull-Up Resistor
HVIO DC Characteristics x
HVIO I/O Pin Leakage Current HVIO Pin Capacitance HVIO Internal Weak Pull-Up and Pull-Down Resistor HVIO Hysteresis Specifications for Schmitt Trigger Input
HPS I/O DC Characteristics x
HPS I/O Pin Leakage Current HPS I/O Pin Capacitance HPS I/O Internal Weak Pull-Up Resistor HPS I/O Hysteresis Specifications for Schmitt Trigger Input
SDM I/O DC Characteristics x
SDM I/O Pin Leakage Current SDM I/O Pin Capacitance SDM I/O Internal Weak Pull-Up Resistor SDM I/O Hysteresis Specifications for Schmitt Trigger Input
I/O Standard Specifications x
HSIO I/O Standard Specifications HVIO I/O Standard Specifications HPS I/O Standard Specifications SDM I/O Standard Specifications
HSIO I/O Standard Specifications x
HSIO Single-Ended I/O Standards Specifications HSIO Single-Ended SSTL, HSTL, HSUL, and POD I/O Reference Voltage Specifications HSIO Single-Ended SSTL, HSTL, HSUL, and POD I/O Standards Signal Specifications HSIO Single-Ended LVSTL I/O Standards Specifications HSIO Differential SSTL, HSTL, and HSUL I/O Standards Specifications HSIO Differential POD I/O Standards Specifications HSIO Differential LVSTL I/O Standards Specifications HSIO Differential I/O Standards Specifications MIPI D-PHY I/O Standards Specifications
HVIO I/O Standard Specifications x
HVIO Single-Ended I/O Standards Specifications
HPS I/O Standard Specifications x
HPS Single-Ended I/O Standards Specifications
SDM I/O Standard Specifications x
SDM Single-Ended I/O Standards Specifications
Switching Characteristics x
Core Performance Specifications Periphery Performance Specifications GTS Transceiver Performance Specifications HPS Performance Specifications
Core Performance Specifications x
Clock Tree Specifications I/O PLL Specifications DSP Block Specifications Memory Block Specifications Local Temperature Sensor Specifications Remote Temperature Diode Specifications Voltage Sensor Specifications
Periphery Performance Specifications x
LVDS SERDES Specifications DPA Lock Time Specifications LVDS SERDES Soft-CDR Sinusoidal Jitter Tolerance Specifications Memory Standards Supported Memory Output Clock Jitter Specifications MIPI D-PHY Performance
GTS Transceiver Performance Specifications x
GTS Transceiver Performance GTS Transceiver Reference Clock Specifications Transmitter Specifications Receiver Specifications Electrical Compliance
HPS Performance Specifications x
HPS Clock Performance HPS Internal Oscillator Frequency HPS PLL Specifications HPS Cold Reset HPS SPI Timing Characteristics HPS SD/eMMC Timing Characteristics HPS USB 2.0 Timing Characteristics HPS USB 3.1 Timing Characteristics HPS Ethernet Media Access Controller (EMAC) Timing Characteristics HPS I2C Timing Characteristics HPS I3C Timing Characteristics HPS NAND Timing Characteristics HPS Trace Timing Characteristics HPS GPIO Interface HPS JTAG Timing Characteristics HPS Programmable I/O Timing Characteristics
Configuration Specifications x
General Configuration Timing Specifications POR Specifications External Configuration Clock Source Requirements JTAG Configuration Timing AS Configuration Timing Avalon® Streaming Configuration Timing Configuration Bit Stream Sizes
Agilex™ 3 FPGAs and SoCs Device Data Sheet

LVDS SERDES Specifications

Table 52.   Agilex™ 3 FPGAs LVDS SERDES Specifications

LVDS serializer/deserializer (SERDES) block supports SERDES factor J = 4 and 8.

DDR registers support SERDES factor J = 1 and 2.

You must calculate the leftover timing margin in the receiver by performing link timing closure analysis. You must consider the board skew margin, transmitter channel-to-channel skew, and receiver sampling margin to determine the leftover timing margin.

For specification status, see the Data Sheet Status table
Parameter Symbol Condition –6 Speed Grade –7 Speed Grade Unit
Min Typ Max Min Typ Max
Clock frequency fHSCLK_in (input clock frequency) True Differential Signaling I/O Standards Clock boost factor W = 1 to 4073 10 — 625 10 — 500 MHz
fHSCLK_in (input clock frequency) SLVS400 I/O Standards Clock boost factor W = 1 to 4073 10 — 445.5 10 — 445.5 MHz
fHSCLK_in (input clock frequency) Single-Ended I/O Standards Clock boost factor W = 1 to 4073 10 — 625 10 — 525 MHz
fHSCLK_OUT (output clock frequency) True Differential Signaling I/O Standards — — — 625 — — 500 MHz
Transmitter True Differential Signaling I/O Standards - fHSDR (data rate)74 SERDES factor J = 4 and 875 76 77 600 — 1,250 600 — 1,000 Mbps
SERDES factor J = 2, uses DDR registers 77 — 50078 77 — 50078 Mbps
SERDES factor J = 1, uses DDR registers 77 — 25078 77 — 25078 Mbps
tx Jitter - True Differential Signaling I/O Standards Total jitter for data rate, 600 Mbps – 1.25 Gbps ≤1,250 Mbps: 160

≤1,000 Mbps: 180

≤800 Mbps: 210

600 Mbps: 240		 ≤1,000 Mbps: 180

≤800 Mbps: 210

600 Mbps: 240		 ps
tDUTY 79 TX output clock duty cycle for True Differential Signaling I/O Standards 45 50 55 45 50 55 %
tRISE and tFALL 76 80 True Differential Signaling I/O Standards — — 160 — — 200 ps
TCCS 74 79 True Differential Signaling I/O Standards — — 202 — — 202 ps
Receiver81 True Differential Signaling I/O Standards - fHSDRDPA (data rate) SERDES factor J = 4 and 875 76 77 600 — 125082 600 — 100082 Mbps
SLVS400 I/O Standards - fHSDRDPA (data rate) SERDES factor J = 4 and 875 76 77 600 — 891 600 — 891 Mbps
fHSDR (data rate) (without DPA)74 SERDES factor J = 4 and 875 76 77 150 — 83 150 — 83 Mbps
SERDES factor J = 2, uses DDR registers 77 — 50078 77 — 50078 Mbps
SERDES factor J = 1, uses DDR registers 77 — 25078 77 — 25078 Mbps
DPA (FIFO mode) DPA run length — — — ≤10,000 — — ≤10,000 UI
DPA (soft CDR mode) DPA run length SGMII/GbE protocol — — 5 — — 5 UI
All other protocols — — 50 data transition per 208 UI — — 50 data transition per 208 UI —
Soft CDR mode Soft-CDR ppm tolerance — –300 — 300 –300 — 300 ppm
Non DPA mode Sampling window — — — 330 — — 330 ps
73 Clock Boost Factor (W) is the ratio between the input data rate and the input clock rate.
74 Requires package skew compensation with PCB trace length.
75 The Fmax specification is based on the fast clock used for serial data. The interface Fmax is also dependent on the parallel clock domain which is design dependent and requires timing analysis.
76 The VCC and VCCP must be on a combined power layer and a maximum load of 5 pF for chip-to-chip interface.
77 The minimum specification depends on the following factors. The differential I/O buffer within the IOE does not have a minimum data rate.
78 You must perform design timing analysis in Quartus® Prime to achieve timing closure and run IBIS/HSPICE simulations to ensure that the I/O buffer's electrical performance meets the interface requirements.
79 Not applicable for DIVCLK = 1.
80 This applies to default pre-emphasis and VOD settings only.
81 When operating in DPA mode, you must enable the receiver equalization feature of the input buffer.
82 1.05 V, 1.1 V, and 1.2 V True Differential Signaling I/O standards on receiver supports data rate up to 1000 Mbps.
83 You can estimate the achievable maximum data rate for non-DPA mode by performing link timing closure analysis. You must consider the board skew margin, transmitter delay margin, and receiver sampling margin to determine the maximum data rate supported.
Level Two Title