HSIO Single-Ended I/O Standards Specifications
HSIO Single-Ended SSTL, HSTL, HSUL, and POD I/O Reference Voltage Specifications
HSIO Single-Ended SSTL, HSTL, HSUL, and POD I/O Standards Signal Specifications
HSIO Single-Ended LVSTL I/O Standards Specifications
HSIO Differential SSTL, HSTL, and HSUL I/O Standards Specifications
HSIO Differential POD I/O Standards Specifications
HSIO Differential LVSTL I/O Standards Specifications
HSIO Differential I/O Standards Specifications
MIPI D-PHY I/O Standards Specifications
HPS Clock Performance
HPS Internal Oscillator Frequency
HPS PLL Specifications
HPS Cold Reset
HPS SPI Timing Characteristics
HPS SD/eMMC Timing Characteristics
HPS USB 2.0 Timing Characteristics
HPS USB 3.1 Timing Characteristics
HPS Ethernet Media Access Controller (EMAC) Timing Characteristics
HPS I2C Timing Characteristics
HPS I3C Timing Characteristics
HPS NAND Timing Characteristics
HPS Trace Timing Characteristics
HPS GPIO Interface
HPS JTAG Timing Characteristics
HPS Programmable I/O Timing Characteristics
I/O PLL Specifications
Symbol | Parameter | Condition | Min | Typ | Max | Unit |
---|---|---|---|---|---|---|
fIN | Input clock frequency source from reference clock input | –6S | 10 | — | 90057 | MHz |
–7S | 10 | — | 62557 | MHz | ||
Input clock frequency source from core clock input | –6S | 10 | — | 41557 | MHz | |
–7S | 10 | — | 35357 | MHz | ||
Input clock frequency source from HSIO clock input | –6S | 10 | — | 71757 | MHz | |
–7S | 10 | — | 62557 | MHz | ||
Input clock frequency source from HVIO clock input | — | 10 | — | 156.2557 | MHz | |
fINPFD | Input clock frequency to the PFD | — | 10 | — | 325 | MHz |
fVCO | I/O PLL VCO operating range | –6S | 600 | — | 3,200 | MHz |
–7S | 600 | — | 2,400 | MHz | ||
fCLBW | I/O PLL closed-loop bandwidth | — | 0.5 | — | 20 | MHz |
fOUT | Output frequency for internal clock (C counter) | –6S | — | — | 1,000 | MHz |
–7S | — | — | 780 | MHz | ||
fOUT_EXT | Output frequency for external clock output | –6S | — | — | 717 | MHz |
–7S | — | — | 625 | MHz | ||
tOUTDUTY | Duty cycle for dedicated external clock output (when set to 50%) | fOUT_EXT < 300 MHz | 45 | 50 | 55 | % |
fOUT_EXT ≥ 300 MHz | 40/45 58 | 50 | 55 58/60 | % | ||
tFCOMP 59 | External feedback clock compensation time | — | — | — | 5 | ns |
fDYCONFIGCLK | Dynamic configuration clock | — | — | — | 100 | MHz |
tLOCK | Time required to lock from end-of-device configuration or deassertion of areset | — | — | — | 1 | ms |
tDLOCK | Time required to lock dynamically (after switchover or reconfiguring any non-post-scale counters/delays) | — | — | — | 1 | ms |
tPLL_PSERR 60 | Accuracy of PLL phase shift | — | — | — | ±50 | ps |
tARESET | Minimum pulse width on the areset signal | — | 10 | — | — | ns |
tINCCJ | Input clock cycle-to-cycle jitter | fREF < 100 MHz 61 | — | — | ±750 | ps (p-p) |
fREF ≥ 100 MHz 61 | — | — | 0.15 | UI (p-p) | ||
tREFPJ | Reference phase jitter (rms)62 | Carrier frequency: 100 MHz with integrated bandwidth of 10 kHz to 50 MHz | — | — | 1.42 | ps |
tREFPN | Reference phase noise63 62 | 10 Hz | — | — | –90 | dBc/Hz |
100 Hz | — | — | –100 | dBc/Hz | ||
1 kHz | — | — | –110 | dBc/Hz | ||
10 kHz | — | — | –120 | dBc/Hz | ||
100 kHz | — | — | –130 | dBc/Hz | ||
1 MHz | — | — | –138 | dBc/Hz | ||
10 MHz | — | — | –142 | dBc/Hz | ||
100 MHz | — | — | –144 | dBc/Hz | ||
tOUTPJ_DC 59 64 | Period jitter for dedicated clock output | fOUT < 100 MHz 61 | — | — | 17.5 | mUI (p-p) |
fOUT ≥ 100 MHz 61 | — | — | 175 | ps (p-p) | ||
tOUTCCJ_DC 59 64 | Cycle-to-cycle jitter for dedicated clock output | fOUT < 100 MHz 61 | — | — | 17.5 | mUI (p-p) |
fOUT ≥ 100 MHz 61 | — | — | 175 | ps (p-p) | ||
tOUTPJ_IO 65 64 | Period jitter for clock output on the regular I/O | fOUT < 100 MHz 61 | — | — | 60 | mUI (p-p) |
fOUT ≥ 100 MHz 61 | — | — | 600 | ps (p-p) | ||
tOUTCCJ_IO 65 64 | Cycle-to-cycle jitter for clock output on the regular I/O | fOUT < 100 MHz 61 | — | — | 60 | mUI (p-p) |
fOUT ≥ 100 MHz 61 | — | — | 600 | ps (p-p) | ||
tCASC_OUTPJ_DC 59 | Period jitter for dedicated clock output in cascaded PLLs | fOUT < 100 MHz 61 | — | — | 17.5 | mUI (p-p) |
fOUT ≥ 100 MHz 61 | — | — | 175 | ps (p-p) | ||
tEINDUTY | Input clock or external feedback clock input duty cycle | fIN ≥ 600 MHz | 30 | — | 70 | % |
450 MHz ≤ fIN < 600 MHz | 35 | — | 65 | % | ||
250 MHz ≤ fIN < 450 MHz | 40 | — | 60 | % | ||
10 MHz ≤ fIN < 250 MHz | 45 | — | 55 | % |
Related Information
57 This specification is limited by the I/O maximum frequency. The maximum achievable I/O frequency is different for each I/O standard and is dependent on design and system specific factors. Ensure proper timing closure in your design and perform HSPICE/IBIS simulations based on your specific design and system setup to determine the maximum achievable frequency in your system.
58 To achieve 5% duty cycle for fOUT_EXT ≥ 300 MHz, you only can use tx_outclk port from the LVDS SERDES FPGA IP. Refer to the Clocking and PLL User Guide for the detail design guidelines.
59 Not applicable for fabric-feeding I/O PLL.
60 PLL phase shift accuracy is 50 ps with the assumption of fVCO = 1.6 GHz.
61 fREF is fIN/N, specification applies when N = 1.
62 Requirement for DDR/LPDDR protocol and LVDS SERDES applications only.
63 The phase noise numbers in this table are the maximum acceptable phase noise values measured at a carrier frequency of 100 MHz. To calculate the phase noise requirement at any other frequency, use the formula: REFCLK phase noise at f (MHz) = REFCLK phase noise at 100 MHz + (20 × log10 (f/100)).
64 This jitter specification does not include the effect of spread-spectrum clock. The magnitude of jitter deterioration is largely depend on the spread-spectrum clock profile used. Refer to the Clocking and PLL User Guide for the recommended spread-spectrum clock profile.
65 External memory interface clock output jitter specifications use a different measurement method, which are available in the Memory Output clock Jitter Specifications table.