Agilex™ 3 FPGAs and SoCs Device Data Sheet

ID 848370
Date 8/11/2025
Public
Document Table of Contents

HSIO Differential LVSTL I/O Standards Specifications

Table 37.  HSIO Differential LVSTL I/O Standards Specifications For specification status, see the Data Sheet Status table
I/O Standard VCCIO_PIO (V) VILdiff(DC) (V) VIHdiff(DC) (V) VILdiff(AC) (V) VIHdiff(AC) (V) VIX(AC) (%)45
Min Typ Max Max Min Max Min Max
LVSTL1146 1.067 1.1 1.133 –0.11 0.11 –0.14 0.14 25
LVSTL10546 1.0185 1.05 1.0815 –0.11 0.11 –0.14 0.14 25
Note: For eye height position estimation in EMIF interfaces, refer to the PCB Design Guidelines: Agilex™™ 3 FPGAs and SoCs. The eye mask estimation methodology defined in the PCB Design Guidelines: Agilex™™ 3 FPGAs and SoCs takes precedence over specifications in HSIO Differential LVSTL I/O Standards Specifications table.
45 Percentage of P-leg and N-leg crossing relative to the midpoint of P-leg and N-leg signal swings.
46 Each sub-bank can only support a single voltage tolerance. The VCCIO_PIO tolerance can be extended to ±5% if the entire HSIO sub-bank is operating in any of the following modes. Else, you must supply the VCCIO_PIO voltage rail with a ±3% voltage supply tolerance.
  • PHYLITE mode
  • GPIO mode